Novel Voltage-sustaining Technology Of Bulk Silicon Lateral Power Device-drift Region Shape Modulation Technology

High voltage LDMOS (lateral double-diffused metal-oxide-semiconductor field-effecttransistors) is one of the key devices of Power Integrated Circuit (PIC). The conflicting betweenon-resistance and breakdown voltage is one of the core problem in power semiconductor devices.Researchers have done enormous and effective work on improvement lateral blocking voltage orlateral electric field optimum. To optimize the lateral electric field in power semiconductor devices,drift region shape modulation technology in bulk silicon lateral power devices is proposed. At thesame time, drift region shape modulation technology is applied in LDMOS, then, two bulk siliconLDMOS structures are proposed to meet lateral electric field optimum, and are investigated basiccharacteristics and fabrication process using semiconductor simulator TCAD tools.First, this thesis proposes a new bulk silicon LDMOS structure with step thickness drift region.Compared with the conventional RESURF device, the drift region is divided into several zones withdifferent thickness increasing from source to drain in this new structure. Owing to modulation effectof the step thickness drift region, new additional electric field peaks are introduced in the driftregion, thus leading to the reduction of the surface electric fields and the increase of the breakdownvoltage. The influences of device parameters on breakdown voltage and specific on-resistance areinvestigated using semiconductor device simulator, MEDICI. The simulation results indicate that an18.4%increase in the breakdown voltage and a42.5%increase in the figure of merit (FOM) areobtained in the new device in comparison with the conventional LDMOS. Then, aCMOS-compatible process with an additional RIE technology is designeded to fabricate the bulksilicon LDMOS. The process conditions and parameters are optimized by using the Silvaco Athena.Second, a novel bulk silicon LDMOS device with partical oxide pillars in the drift region isproposed. In this new structure, the oxide pillars are introduced in the drift region, thus leading tothe drift region width increasing from source to drain in this new structure. Owing to modulationeffect of the oxide pillars, the surface electric fields are improved and the breakdown voltage isincreased. The influences of device parameters on breakdown voltage and specific on-resistance areinvestigated using semiconductor device simulator, DAVINCI. The simulation results indicate thatan16.7%increase in the breakdown voltage and a25.3%increase in FOM are obtained in the newdevice in comparison with the conventional LDMOS. Then, a CMOS-compatible process with anadditional STI technology is designeded to fabricate the bulk silicon LDMOS without additional masks. The process conditions and parameters are optimized by using the Sentaurus Sprocess.