Research And Design Of Ultra-low Temperature Superconductor-CMOS Interface Circuit For Quantum Computing

In recent years,with the development of superconducting technology,superconducting quantum computers have provided new ideas for the design of high-performance processors and have shown great potential.Quantum computers need not only fast signal processing capabilities,but also large-capacity data storage capabilities.However,due to the low integration density and low drive capability of superconducting,large-capacity superconducting memory has become a bottleneck restricting its development.Compared with existing superconducting memory circuits,static random access memory circuits(SRAM)based on mature CMOS technology have huge advantages in area and drive capability.Therefore,the superconducting-CMOS hybrid architecture provides a better solution for the large-scale integration of Rapid single flux quantum(RSFQ).The superconducting routing Josephson structure generates RSFQ signal under 4.2 K temperature environment,and its output signal has the characteristics of low swing,low duty cycle and non-return to zero code.However,the CMOS SRAM circuit usually requires the input signal to be a full-swing return-to-zero code.Obviously,there is no direct signal transmission between the RSFQ circuit and the CMOS circuit.Therefore,the establishment of a very low temperature interface circuit between superconducting and CMOS memories has important theoretical and practical application values.Thesis first studied the working principle of RSFQ logic circuit through simulation,analyzed the low-temperature characteristics of CMOS devices and low-temperature SPICE model,designed a very low-temperature superconducting-CMOS interface circuit based on 55 nm CMOS process,and finally verified it through tape-out testing.The main content and innovations of this thesis are as follows:1.Thesis proposes two amplifying circuits at 4.2 K ambient temperature-source follower amplifying circuit and high-speed static comparison amplifying circuit,both of which can amplify 1 GHz and 20 m V signals with low delay.The input stage of the source follower amplifying circuit is a source follower,which relocates the signal.The high-speed static comparison amplifier circuit uses a cross-coupled static comparator as the gain stage.The source follower amplifier circuit has a 1 V-1.4 V power supply voltage range,and it also has low transmission delay and power consumption.The high-speed static comparison amplifier circuit has high gain,the gain reaches 35 d B at 1 GHz,and it also has the characteristics of high PSRR.2.Thesis proposes an RZ-NRZ converter,which extracts the phase of the data and distinguishes it from the CLK phase,then processes the data or CLK t o align the phases of the two,and finally uses the processed signal for sampling and output.Supports all phase differences.It has two modes,namely synchronous mode and asynchronous mode.The delay time corresponding to the two modes is different,and different modes can be selected according to different requirements.3.Thesis proposes a fast transient response LDO.When the load current changes in steps of 20 m A / 100 ns,the undershoot and overshoot are 0.16 m V and0.33 m V,respectively,and the transient response time is 116 ?s.The superconducting interface circuit designed in this thesis is designed with 8 parallel channels and the circuit area is 2300 ?m×800 ?m.In the post-simulation verification,the input signal frequency is 1 GHz,the signal transmission delay is 700 ps,and the overall circuit power consumption is 13 m A.After passing the 55 nm CMOS process,it was successfully tested in a 4.2K environment.