Research On Low Voltage Low Noise Amplifier With CMOS Technology

With the development of wireless communication technologies, high integration and miniaturization have become main demands and characteristics of wireless communication. One technology towards high integration and miniaturization is that all circuits are integrated into one package system to weaken the requirement of peripheral circuits and devices for the goal of miniaturization. In the highly integrated package system, the electric energy will be partly transformed into heat energy which is the potential risk for the whole system. For this reason, power dissipation is the crucial issue. Radio frequency integrated circuits (RFIC) based on CMOS technology have taken their main position in package system due to low cost and high integration. For all devices and circuits in a package system, the power dissipation increases quadratically with the supply voltage, thus, lowering the supply voltage is one of effective approaches to reduce device power dissipation. At the same time, many implantable medicine telemetries, wireless remote sensors generally operate at ultra-low supply voltage with a small battery or environment energy. For this case, it's required the whole system or wireless device can be normally operating at an ultra-low voltage. However, for RF front-end, the key part of these systems, low operation voltage will result in poor performances, even out of operation. On the other side, personal wireless communication development has required the high transfer rate and big bandwidth. However, conventional low frequencies carriers can't meet this goal due to the crowded wireless bandwidth resource. Low transfer rate and narrow bandwidth have constrained the development of wireless technologies. The conflict between crowded frequencies resources and requirement of big bandwidth has accelerated the trend of higher operating frequency.Based on above reasons, low voltage CMOS RFIC and high frequency CMOS RFIC, which can be implemented into system in package, have been studied in this dissertation. Firstly, the low voltage low power technology for cascode low noise amplifier (LNA) widely used in RF front-ends due to its high reverse isolation has been studied in chapter 2. Since the NMOS is arranged as the stacking structure, it's hard to be operated properly at low supply voltage. Furthermore, since the current consumption is tightly related to its RF properties, lowering the consumed current will generally results in degradation of RF properties. To overcome these difficulties, direct current (DC) split and forward-body-bias (FBB) technology has been used to lower the supply voltage and current consumption simultaneously, thus, the whole power dissipation has been decreased. The design of the low voltage cascode LNA is studied in details and verification circuit is fabricated and measured. And the availability of this approach has been verified by experimental results. Experimental results show that the designed low voltage cascode LNA can operate at 0.5 V supply voltage and its power dissipation is decreased to around 30% of the conventional cascode LNA while all RF characteristics are comparative to those of conventional cascode LNA.For LNA, cascaded-stage structure composed of single stage is another popular topology. In the chapter 3, the relationship between noise figure, gain and operating frequency of single stage has been firstly investigated, which provides the theoretical guidance of cascaded-stage LNA design. At the same time, the gate-drain capacitance of NMOS transistor constituting the feedback path of signal has negative effects to input match and gain. These influences have also been investigated and implemented into analysis and design of cascaded-stage LNA. Based on the investigation and FBB technology, a 0.5 V X band LNA has been designed, fabricated and measured. The measured results illustrate that the power dissipation of the designed X-band low voltage LNA has been steeply decreased with comparative RF performances. To further reduce the power dissipation of cascaded-stage LNA, the current-reused technology has also been combined with the FBB technology. Details for design and optimum bias technique have been investigated to further decrease the current consumption, which is verified by the realized circuit.Compared with other III-IV substrate, substrate of CMOS technology is of low resistivity and low transit frequency. When the circuit's operating frequency is up to K-band, conventional multi-gigahertz CMOS RFIC approaches will be confronted with its bottleneck. High-frequency CMOS circuit design is a challenge. In chapter 4, the optimum bias technology and gain boosting technology on K-band (21 GHz) low voltage LNA are investigated. Depending on optimization of gate bias, the conventional bias optimization technology for linearity with low gain and narrow adjustment range has been avoided. At the same time, by weakly negative feedback technology in the first stage, the gain is increased without cost of power dissipation. Experimental results illustrate the availability of the analysis and design.K-band CMOS highly integrated single chip T/R system can be widely applied in wireless interconnection on chip and automotive radar while its high integration requires the low power dissipation characteristic for each sub-system. In chapter 5, low power 24 GHz RF front-end of receiver is investigated. The system architecture and its performances are studied. Then, the strategy of lowering system's current and their proposed topology are investigated and whole system performances are finally simulated. Simulation results show the proposed system has the lower power dissipation with comparative RF performances.