Design Of High Speed And High Precision Reference Voltage Buffer Circuit For Time Interleaved ADC

In analog circuit design,stable reference voltage is often needed.Reference voltage module is widely used in digital-analog hybrid circuits.With the improvement of semiconductor technology,the speed of digital circuit is faster and faster.In high-speed digital-to-analog conversion system,not only the reference voltage is required to have high accuracy,but also the high-speed transient response capability is required.The traditional reference voltage circuit adopts a closed-loop linear regulator structure,which uses the loop bandwidth and lager capacitance to ensure the stability of the output voltage.However,with the acceleration of signal sampling rate,the traditional loop bandwidth is difficult to meet the response speed requirements.At the same time,the influence of parasitic inductance packaging on the response speed is becoming more serious.Based on the theoretical analysis of high-precision reference voltage and high-speed analog-todigital converter,a high-speed and high-precision reference voltage buffer circuit for high-speed time interleaved ADC is designed in this paper.A high-speed and highprecision reference voltage buffer circuit with excellent performance is realized at 4GS/s sampling rate by combining the former high-precision reference source with the latter open-loop buffer output stage structure.Firstly,the working principle of bandgap reference is analyzed,and the requirements for bandgap reference are proposed.A bandgap reference circuit with temperature compensation is designed,which can provide high precision reference input voltage and reference input current for reference voltage buffer circuit with low temperature coefficient in the temperature range from-40?~125?.Secondly,because the reference voltage buffer designed provides reference level for high-speed TIADC in this study,the process of load transient response is more complex.In this paper,the reference voltage buffer transient response of the load channel ADC in each quantization switch switching process is carefully analyzed,according to the analysis results,a more clear design method is proposed.In this paper,a new type of buffer output structure is adopted,which takes into account power consumption,speed and accuracy better than some traditional structures.The overall reference voltage buffer adopts the master-slave structure.The influence of gain mismatch caused by the deviation of reference voltage of each branch on the interleaving performance of multi-channel is obtained by modeling and simulation.The optimal CRC network for eliminating kickback noise between channels is obtained by reasonable design of output stage tube size and simulation to reduce the influence of reference voltage buffer on the overall TIADC performance.Finally,the post-simulation of the circuit is completed by using Cadence design platform,Spice simulation tool and Laker layout design tool under 40 nm CMOS process.The simulation results show that the low-frequency PSRR of the front bandgap is 80 dB,the temperature coefficient is 18 ppm/? and the output noise is 115.36?V.When the input signal frequency is 1.5GHz and the sampling frequency is 4GHz,the SFDR is 82.36 dB,SNDR is 71.86 dB and ENOB is 11.64 bit.