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Research And Verification Of BOOT Module In SOPC System Based On UVM

Posted on:2020-10-22Degree:MasterType:Thesis
Country:ChinaCandidate:H Q LiuFull Text:PDF
GTID:2428330602952298Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the increasing design capability of integrated circuits and manufacturing technology,the scale of integrated circuits has gradually expanded,and the integration of electronic components on a single chip has already exceeded 1 billion.In this case,the correctness,completeness and reliability of the chip verification become the focus and difficulty of the verification work.In order to discover all the problems in chip design as early as possible,and reduce the time cost of chip design and manufacturing,the efficiency and completeness of chip verification have attracted much attention.The strong demand for chip verification has led to the continuous updating of verification techniques and methods,and the UVM verification methodology was then proposed.In this paper,the core ideas and platform structure of UVM verification methodology are studied in detail,and the advantages of UVM in platform reusability,portability,flexibility and high efficiency are fully introduced by analyzing the Universal Verification Component,Verification mechanism,communication process,register model and other aspects.This paper takes the BOOT startup module in a SOPC communication chip project as the verification object during the internship.The focus of the work is to build a reusable verification platform using UVM verification methodology.Firstly,the APB and AHB bus protocols used in the BOOT module work are studied,and their read and write operation timings are described in detail.Then,the structure and function of the BOOT module and its connection relationship with the peripheral modules are fully studied and analyzed.According to the usage scenarios and workflows of the moving and reading functions,and the abnormal use,all functional test points of the BOOT module are extracted.After that,according to the UVM methodology,the implementation strategy of the verification platform is established,the platform UVC component is built,the communication between the UVC components is completed,and the verification platform of the BOOT module is built.The development of test incentives,the establishment of register models,the drive implementation of each level and the self-contrast mechanism are the focus of this paper.Because the UVM platform is built with more modular components,all common protocol components such as APB and AHB in this verification platform can be directly transplanted into other similar functional module platforms,reducing code writing,improving verification efficiency,and reducing verification costs.After the verification platform is completed,the whole process of the debugging process of the verification environment and the output from the compilation to the verification result is described in detail.At the same time,for the three types of function points of moving,reading and abnormal,three functional test cases are listed to analyze the simulation results,which ensure the correctness of the verification results.Then use VCS software coverage collection tool to collect and analyze the overall code coverage and functional coverage,analyze and explain the code coverage uncovered parts,and finally verify the results meet the project requirements,code coverage rate of 90% above,the code line coverage is over 95% and the function coverage is 100%.After the BOOT module verification,this paper summarizes the problems encountered in the verification process and its own shortcomings,and expounds the aspects that need to strengthen learning in the future work.
Keywords/Search Tags:UVM verification methodology, APB, AHB, coverage analysis, module level verification platform
PDF Full Text Request
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