A Block-level Verification On Audio Module Of MHL-to-HDMI Dongle Based On UVM

With the development of integrated circuit technology, it has been integrated billions of microelectronic devices in single chip. In this environment, how can we ensure the accuracy and the consistency of chip, how to provide the most convenient means of verification for the design team, which is a serious problem that verification engineers have to face. And it is a key to the success of modern chip design. More and more people devote into the verification work, prompting the UVM verification methodology.The verification platform architecture based on UVM and the classification, structure and function of main component UVC(Universal Verification Components) have been studied in detail in this paper.This paper takes the AUDIO module in a MHL-to-HDMI Dongle chip based HDMI(High Definition Multimedia Interface) interface Specification as the design under test. The core of this paper is how to use the way of UVM to build a reusable block-level verification environment of AUDIO module with System Verilog verification language. According to the feature of AUDIO module and the analysis of its external environment, this paper has separated the function test point. According to the thought of UVM, this paper has formulated the implementation strategy of block-level verification environment of AUDIO module. This paper focuses on the establishment of test case library, the building of sequence library, the implementation of the powerful driver and the contrast mechanisms of input data and output data.In the simulation, this paper has analyzed the simulation waveform about the representative test case, and determined the correctness of AUDIO module ultimately.What's more, this paper has analyzed the result of code coverage and functional coverage,the former is 96%, the latter is 100%.The coverage has satisfied the project requirement.This block-level verification environment can be transplanted to the subsystem or system-level verification environment, and uses fewer test cases and shorter time to complete the verification task.