Thermal Stress Analysis And Optimization Of Through-silicon Via(TSV)

Nowadays,the fast-developing electronics industry puts forward higher requirements on microelectronics technology,and it is hoped that the functional density and performance of microsystems will continue to improve.As the feature size of integrated circuit devices is approaching physical limits,for the continuation of Moore's Law,new devices and three-dimensional integrated circuit(3D IC)have provided new ideas for solving the problems in traditional integrated circuits.So far,the development has entered the Moore.era.Through-silicon via(TSV)technology has a disruptive impact on the pattern of integrated circuit technology.TSV maximizes the stacking density of chips in the three-dimensional direction and is considered to be one of the best solutions for 3D IC interconnection.TSV not only brings good opportunities,but also new challenges.The most significant problem is the thermal stress caused by the mismatch of thermal expansion coefficients between materials.Excessive thermal stress can lead to reliability problems such as circuit function failure and device performance drift.How to effectively reduce the TSV thermal stress and the keep-out zone(KOZ)introduced in the substrate has become an urgent problem to be solved.In order to analyze and optimize the stress introduced by TSV,this paper is based on cylindrical TSV(C-TSV),modeling and simulation in ANSYS Workbench software,using the idea of finite element method to analyze its material characteristics,structural parameters and thermal stress annular shallow trench isolation(A-STI),square and circular trenches,and metal layer partially filled annular TSV(A-TSV)structure are proposed to effectively reduce the stress on the substrate surrounding TSV,thereby improving the integration;the model of double-layer single C-TSV with groove structure in face-to-face and face-to-back bonding methods is established.For C-TSV,the von Mises stress conditions under different combinations of thickness and material are compared,and the results show that the BCB dielectric layer can effectively reduce the stress introduced by the TSV copper pillar,and the material characteristics have a greater impact on the stress,and the increase in thickness is the benefit limited.The higher the annealing temperature,the greater the stress introduced by the TSV.Compared with C-TSV without A-STI,when the pMOS channel direction is perpendicular to the stress direction,A-STI reduces KOZ by 13.6%;when the nMOS channel direction is parallel to the stress direction,A-STI reduces KOZ by 15.4%.When the depth of the square trench is 2?m,most of the stress can be intercepted in the trench,while the depth of the circular groove needs to be 5?m to have similar results.Because the stress introduced by TSV is petal-shaped,and the similar shape of the square trench is more in line with the stress distribution.In general,the square trench reduces KOZ by 70.94%,and the circular groove reduces KOZ by 69.36%.For A-TSV,compare the von Mises stress when the dielectric layer and the oxide layer are filled with different materials.Compared with the filling of SiO2,when the metal layer is filled with BCB,the thermal stress induced by TSV will increase;when the outside of the metal layer is BCB,it will reduce stress.Compared with C-TSV,A-TSV can reduce KOZ by up to 24%.In the double-layer single C-TSV model,comparing the von Mises stress in different areas,the stress concentration area is located on the micro-bump,specifically where the bumps are in contact with the substrate and the bonding layer.Compare the maximum stress of the bump under different radii,the maximum stress on the lower surface of the upper C-TSV,and the maximum stress on the upper surface of the lower C-TSV.When the radius of the micro-bump is 6?m,the above stresses all reach the minimum.