Design Of Multistandard Wideband RF Receiver For Digital Radio In Deep Submicron CMOS Technology

The digital radio broadcasting standards, including Digital Radio Mondiale (DRM) and Digital Audio Broadcasting (DAB), are pushing forward the audio broadcasting from analog mode to digital mode. A digital radio can not only improve the audio quality, but also offer additional services, like text and images. Therefore, the digital radio is the future of the conventional radio broadcasting. This thesis presents an integrated wireless receiver for both DRM and DAB. Following novel techniques are proposed in system and circuits design.1) The analysis and design of the receiver’s architecture is presented. Various receiver topologies, like direct conversion and superheterodyne, are analyzed. Based on the analysis, a dual-conversion low-IF architecture with a fixed 1st IF is proposed. According to the DRM and DAB standards, the specifications of the receiver, like the noise figure (NF), the linearity and the image rejection ratio (IRR), are derived. Then, the specifications of each building block are estimated by simulation tool.2) A novel capacitive cross coupling common-gate (CG) low-noise amplifier (LNA) with wide bandwidth and high linearity is presented. First, we presented the principle and design of a conventional CG LNA. To improve the LNA’s bandwidth and linearity, we proposed a gate-active-inductor technique and a derivative superposition technique. The differential active inductor is connected to the cascode transistors’gates directly that can also provide a DC bias voltage. The LNA is fabricated in SMIC’s 0.18-μm RF CMOS process, and the measurement results show that the proposed techniques are effective in improving bandwidth and linearity.3) A novel wideband mixer based on current mirror topology is proposed. The advantages and disadvantages of various mixers, like the Gilbert type and the passive type, are analyzed firstly. Then, we proposed a low-voltage current-mirror mixer with high 2nd order input intercept point (IIP2). A current-reuse technique and a current-bleeding technique are both employed in the transconductance stage to achieve a large transconductance but a low second-order intermodulation. The linearity of the voltage-mode passive switching stage is also analyzed first. The mixer is fabricated in SMIC 0.18-μm RF CMOS process, and the measurement results show that the proposed techniques are effective. The mixer’s supply voltage is only 1 V, what is suitable for low voltage operation.4) A novel programmable gain amplifier (PGA) based on signal-summing topology is proposed. The advantages and disadvantages of various variable gain amplifiers (VGA) and PGAs are analyzed firstly. Then the signal-summing VGA is modified into a PGA. The signal-summing VGA changes the gain by changing the bias voltage to redistribute the current. We change the current through controlling the aspect ratio of the transistors binarily. This technique helps us to achieve an accurate 6-dB step size. To obtain accurate initial gain, constant-gm bias technique is also employed. The input transistors and the load resistors in the PGA and the bias circuits are the same kind, therefore, the product of the transconductance and the load resistors is constant, independent of process, voltage and temperature (PVT). A source degeneration technique is also employed to improve the linearity at low gain. The PGA is fabricated in SMIC 0.18-μm RF CMOS process, and the measurement results show that the proposed techniques are effective.5) A complex filter for IRR is also presented. A 3rd-order Chebyshev leapfrog active-RC topology is chosen as the low-pass prototype. Two mainstream frequency calibration technique, PLL method and time constant method are introduced. We proposed a simple calibration scheme based on time constant method. The flow chart of the calibration process is also presented. The complex filter is fabricated in SMIC 0.18-μm RF CMOS process, and the measurement results show that the filter can offer good IRR and has an accurate frequency response.6) DC offset cancellation (DCOC) and automatic gain control (AGC) are also studied. There are two main DCOC techniques, including analog DCOC (ADCOC) and digital DCOC (DDCOC). Although the ADCOC has a simple circuit, it will affect the PGA’s noise and frequency response. Especially in noise, the ADCOC’s noise will deteriorate the PGA’s noise directly. The bandwidth will be reduced and the gain error will be increased. An effective optimization technique is proposed by increasing the offset amplifier’s gain and offset resistor simultaneously. The scheme of a DDCOC is more complex, but it will affect the PGA’s performance little. Therefore, a DDCOC is adopted in the final design. A simple AGC circuit based on both analog and digital techniques is also proposed. Only one rectifier and two low-power comparators are employed with a digital control circuit. The whole circuit is fabricated in SMIC 0.18-μm RF CMOS process, and the measurement results show that the DDCOC and AGC are effective.7) The other building blocks, including 2nd-IF mixer and frequency synthesizer are also presented. The integration of the signal processing chain and the phase-locked loop (PLL) comprise the complete DRM/DAB receiver. The measurement results show that this integrated wireless receiver can demodulate DRM and DAB signals.