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Reacarch On IR Drop Analyse Of SOC Low Power Chip Design

Posted on:2016-07-16Degree:MasterType:Thesis
Country:ChinaCandidate:X J HeFull Text:PDF
GTID:2308330482953295Subject:Software engineering
Abstract/Summary:PDF Full Text Request
The IT technology develops so quickly recent years that WEB-based terminal mobile devices update for nearly every year and market requirements for their core chips become more and more rigorous. With the performance of mobile chips improve, the power dissipation increases as well. Consider the limitation of the battery, different kinds of low-power design of chips are widely used during manufacturing. In application of the low-power design, we mainly utilize the power saving mode to extend the working time of chips and efficiently balance the working performance, power dissipation and heat radiation. Nowadays, there are many challenges in front of IC designers with the extension of design scale and improvement of processes In high speed circuit, the crosstalk noise caused by coupling capacitance between metal interconnects can lead to a large amount of timing violation or even logic errors and IR drop does much harm for the entire performance of chips, sometimes crash the chips when severe. As a consequence, back-end IC designers spare no efforts to avoid the negative effects of crosstalk noise and IR drop of source.In this article we analyze the IR drop problem of chips which are designed by the low-power design method, the EM problem and the realistic application of the electrostatic protection inspection of ESD as well with the help of using Redhawk which is developed by Apache.In order to introduce the low-power design method, we firstly discusses the different methods of analyzing the power dissipation by using PTPX from Synopsys, quiescent dissipation analysis and dynamic dissipation analysis included. Secondly we introduce some kinds of usual method based on the low-power design, including the design of clock gating, multi voltage domain, power supply transfer switch, isolated location, reserved registers, UPF document and their principles of work.In next part of this article, we give description of the P/G grid, introduce the cause of IR drop and electromigration and the importance of analyzing them. After theintroduction, we use Apache’s Redhawk tool to check the voltage drop and electromigration(EM) in detail, give definition to the input file and configuration parameters Then we give detailed design method of operations focus on multi voltage domain, power gating control analysis, IP module analysis with power switch, RAM design and analysis with switch and principle of ESD protection mechanism including the test method in particular project.In last part of the article, we list out and analyze the test result data captured by giving IR drop analysis, electromigration and ESD protection test. Summed up the problem with the process of the project that may be encountered during the inspection, amend method and other research prospect that need to be drew attention in advance.
Keywords/Search Tags:SoC, IR drop, ESD protect, EM, low power design
PDF Full Text Request
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