Research And Implementation Of Digital Back-end Power Optimization Technology For A 40 Nm IC

With the progress of IC manufacturing technology and the increaseing demand for computing power.The number of integrated transistors per unit area is increasing.The huge power consumed by the high-speed operation of the circuit has become a major problem limiting the chip applications.Low power design is a great challenge for IC industry.From the level of digital back-end design,this paper studies the corresponding power optimization technology to realize the power optimization of a 40 nm chip.An efficient multi-bit Flip-Flop merging algorithm is proposed,which is embedded in the back-end design process.This method simplifies the clock tree structure,and completes the merging of 53.53%Flip-Flops in the chip,and optimizes the total routing length by 20.16%,and reduces the power of the clock network by 26.33%.Then a net weighting method combining power weight and timing weight is proposed,which optimizes the load capacitance of the key data path and reduce the total switching power of the chip by 20.63%.Finally,based on the traditional digital back-end process,a design process for optimizing power is proposed,and the digital layout design of the chip is completed,which reduces the total power of the chip by 15.42%.The main innovations of this paper are as follows:1.Combine the physical location information and timing information of the single-bit Flip-Flops to identify the mergeable area of the single-bit Flip-Flops.An adjustment factor is added to the algorithm to take into account the merging range and accuracy of multi-bit Flip-Flops,so that the merging process can be embedded in different stages of digital back-end design.2.An algorithm for multi-bit Flip-Flop clusters based on the edge of Flip-Flop is proposed,which reduces the number of nodes calculated by 1 times compared with the traditional method.The efficiency of the algorithm is greatly improved.3.An efficient algorithm for solving the optimal merging sequence is proposed,which can quickly solve the optimal multi-bit Flip-Flop merging sequences under the thriple constraints of power consumption,timing,and routing resources.4.A net weighting method is proposed,which uses the power weight to quantify the net toggle rate,and the timing weight to quantify the timing slack of the net,which optimizes switching power and reduces the impact on circuit timing.The research results of this paper are not only applicable to the power optimization of the 40 nm chip,but also have application value and reference significance for the power optimization of digital back-end design.