Low-power Technology In The Back-end Design

With the development of IC fabrication techniques, the speed and integrity of the chip increase greatly, which makes the power density increase dramatically. In order to prolong the battery life of the portable device and decrease the cost of package, the power consumption should be considered in chip design and implementation. With the increase of chip size, there are too much workload with schematic/layout entry, which makes the EDA tools pretty necessary. Embedded microprocessor is the core component of SoC, So the design of low power embedded microprocessor is one of the most important research areas.Based on the analysis of the IC power consumption, the dissertation studies the usual low power design techniques and gives the low power design flow in this work, which analyzes and optimizes the power consumption with EDA tools, and makes power lower.Two design flows are illustrated in this work,1) a general digital design flow based on SYNOPSYS EDA TOOL , such as DesignComplier , Astro , PrimeTime , to realize low power design flow with multi-vt technique, including multi-vt cells, gated clock.2) a general digital design flow based on SYNOPSYS EDA TOOL , such as DesignComplier , Astro , PrimeTime , to realize a low power design flow with multi-supply voltage(MSV), which could decrease both dynamic power and leakage power greatly.