Design And Verification Of A Transparent Interconnection Component Between Multiple Chips

By using multiple processors to form an array for multi-core collaborative parallel computing,the data processing capability of the system can be doubled.When the chips are connected in pairs,high-speed interfaces such as PCIE,Rapid IO,Ethernet,etc.are mostly used to achieve point-to-point connection.However,for multi-chip interconnection,the system needs to be interconnected through a switch chip.A switching chip can only correspond to one high-speed bus protocol,and there are problems such as high hardware cost,poor flexibility and cumbersome configuration.In view of this situation,combined with the needs of the FT-X DSP project,this article proposes an FT?Link interface,which combines on-chip network and high-speed interconnect bus technology,and can effectively solve the expansion and communication problems between chips.This subject targets the contradiction between the functional requirements of multi-chip interconnection and the inability of the original high-speed interface to process multi-chip and multi-host requests,it develops research on the design and verification technology of the FT?Link high-speed interface for inter-chip interconnection.This paper puts forward dimension order module innovatively,it is used to ensure the consistency of request sequence and response sequence of multiple DSP hosts.In order to simplify the engineering configuration steps,an address mapping module is proposed.The implemented FT?Link interface not only supports the original high-speed interface transmission method,but also completes the interconnection of multiple chips,and can transmit requests transparently between multiple chips(users can use multiple chips as one chip).The FT?Link interface proposed in this article is divided into three parts,including network extension interface design,network-AXI transition bridge design and Rapid IO core design.The network expansion interface design realizes the multi-chip routing design,and completes the hardware routing mechanism between multi-chips on the network.Network-AXI transfer bridge designed dimension sequence module in order to ensure the strong order between the requests of the multi-chip interconnection system in the data transfer process.In this module,this article innovatively designs an enhanced FIFO to ensure the correctness of the request transmission.On the basis of the original IP,the Rapid IO core designed an address mapping module and optimized the register configuration steps;improved the serious error handling module,which can prevent the host from failing to receive the response information and cause downtime,significantly improving the stability of the system.The problem studied in this paper comes from the problem of multi-chip interconnection within the embedded system.This paper designs a transparent interconnection component FT?Link between multiple chips by analyzing the existing high-speed bus protocol.The interface can realize the interconnection of multiple chips without exchanging chips,and the interconnected system can be used as a chip.Under the condition of dual-chip interconnection,when the FT?Link is configured as four channels,the maximum effective bandwidth of the link can reach 14.9Gbps.The test and comprehensive results show that the FT?Link technology obtains the function of transparent interconnection of multiple chips with a higher throughput rate and lower delay under very small hardware overhead.