Researches On The Key Technologies Of Double Chennel Serial RapidIO Communication Interface

With the development of the modern microprocessor and the embedded system on chip,the performance of the traditional system bus can no longer meet the commands,the RapidIO protocol is currently the only embedded system interconnection standards in the world,compared to other bus interface,RapidIO is equipment of high bandwidth,low latency,high reliability,good extensibility and flexible interconnection.The single channel maximum transmission rate of RapidIO 2.0 and RapidIO 3.0 protocol is up to 6.25 Gbps and 12.5Gbps.RapidIO can meet the requirement of high-speed data transmission in different application scenarios.The existing single channel RapidIO supports 3 kinds of lane mode(1x,2x,4x).In the case of using 1x or 2x mode,the others are in idle while only 1 or 2 lanes works for data-transmission,what's more,one RapidIO can merely be connected with one destination,both of which brings a result of unnecessary bandwidth wasting.At the same time,with the development of RapidIO protocol,high speed SerDes are needed to provide higher bandwidth,therefore,the research and implementation of the higher protocol version of RapidIO circuit is imperative.Based on the above two aspects,this paper conducts relevant research around RapidIO high-speed interface.The main work is as follows:1.Based on the serial RapidIO protocol,a serial RapidIO interface that supports double-channel transmission was proposed and designed via various functional optimization of existing IP,improves the flexibility and transmission bandwidth of RapidIO system interconnection.The configurable cross switch in Physical Coding Sub-layer was designed to realize 14 transmission modes.In double-channel mode,it can be connected with two RapidIO interfaces.The simulation verification was carried out with NC Verilog,the transmission performance of the system were analyzed and evaluated.Experimental results show that in 1x or 2x mode,the bandwith of double-channel transmission is twice of tranditional design,at the same time,in 4x mode,the effective bandwith of double-channel RapidIO is the same as that of tranditional single-channel RapidIO,which proves that double-channel RapidIO has obvious advantages over single-channel RapidIO in transmission bandwidth.2.According to the demand of 12.5Gbps SerDes for Physical Coding Sub-layer and the protocol definition of Physical Coding Sub-layer in RapidIO 3.2,the 64b/67 b PCS layer circuit applicable to 12.5Gbps link was designed.Among them,the sending channel mainly includes output channel data allocation,scrambler,64b/67 b encoding and rate conversion circuit(67b to 32 b,32b to 67 b,32b to 64b).The receiving channel mainly includes codecode boundary lock,67b/64 b decoding,IDLE3 decoding,descrambler,channel synchronization,multi-channel alignment,linkinitialization and other sub-module.Finally,NC Verilog was used for simulation verification,and the verification results were analyzed.Verification results show that compared with the existing RapidIO2.1 8b/10 b PCS circuit,64b/67 b PCS circuit can support faster link transmission and has stronger link control ability,and the circuit conforms to the RapidIO3.2 protocol definition.