Research On MCU Low Power Design Based On 40nm Process

In today's Post-Moore law period,the high-performance and low-cost advantages brought by Microcontroller Unit have entered thousands of households.With the coming of the Internet of Things era,the performance requirements of ordinary users have been better met.Users have begun to pursue the convenience brought by the Io T technology.One of the core technologies of the Io T terminal is the Low-power technology.Since the energy of micro Io T terminals can only come from limited sources such as batteries or energy harvesting,the energy consumption of the terminals is limited.Therefore,before a breakthrough in battery is achieved,it is necessary to optimize power consumption in various chips used in Io T terminals,especially the MCU as the core controller,to extend the terminal usage time as much as possible and improve user experience.The main work of this thesis is the low-power design of the MCU based on 40 nm process.The thesis firstly analyzes the dynamic power and static power of the MCU in detail.Based on this,the parameters that affect the MCU power consumption level are obtained,and the method of MCU power evaluation is studied.On the basis of that,the thesis has studied the principles and application methods of several types of MCU low-power design technologies in detail,including multi-voltage design,power gating,clock gating,low-power clock tree synthesis technology and switching power supply application.Finally,the above methods are applied in the MCU design process.The design first divides the MCU into voltage domains and power domains,and divides six voltage domains and four power domains according to function and performance requirements.Next,the overall power consumption of the MCU is analyzed.According to the power report reported by the Voltus tool,the module that generates redundant power is identified and the redundant power is almost eliminated by clock gating.The SRAM is divided into blocks.The blocks which are not read or written are gated by address signals.SRAM related power is reduced by about 46.22%.Entering the backend design stage,the clock concurrent optimization technology is used to replace the traditional clock tree synthesis process during clock tree synthesis phase,and the transition time constraints and clock skew are appropriately relaxed.The clock tree power in the MCU has been reduced by nearly 8.18%.After the switching power supply is adopted,the power supply of the MCU becomes a switching power supply and an LDO regulator in series.Benefit from the energy conversion efficiency of the switching power supply of nearly84%,the total power of the MCU has been reduced by nearly 33%.Finally,the problem of large driving units and long traces in the layout is optimized,and the power optimized about6% of the total power.The simulation results show that the low-power design method in this thesis can effectively reduce the overall power consumption of the MCU,which has certain engineering practical significance.