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Low Power Digital Integrated Circuit Design

Posted on:2009-12-18Degree:MasterType:Thesis
Country:ChinaCandidate:W D JiangFull Text:PDF
GTID:2178360242489986Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the development of IC design technology, the speed and integration of chips have been greatly improved, however the power consumption of unit area is increasing. Every IC designer should consider the power consumption in his design. The low power design is becoming one of the most important jobs in every IC design company. In this paper, the research on origin and calculations of power consumption of the digital integrated circuits are made, meanwhile some methods of reducing the power consumption in the design levels of system-level, algorithm-level, register-transfer-level, gate-level, layout-level and circuit-level are given. The software of Design Compiler and Prime Power developed by Synonpsys are used to make the analysis of area and power consumption of certain circuits. The results of the analysis are very important for the design of digital integrated circuits.First, background of the research and actuality of low power design in digital IC both in and out of the country are presented. Then, the methods of estimation and optimization of power consumption are given. The optimization methods of power consumption in gate-lever and register-transfer-level are mainly discussed, and the optimized results are got from the expriments on certain circuits using different optimization methos. In the gate-level low power design, the methods of cell mapping and common factor extracting are proved to be effective with EDA tools, and get the optimized results of simple logic circuits to standard cells based on TSMC 0.18um technology through cell mapping. In the register-transfer-level, the method of clock-gating is proved to be effective in certain circuits with EDA tools, and get the optimized results of common circuits using the method of clock-gating. And also, it's demonstrated that Code Style can also affects the area and power consumption of the circuits mapped. At last, low power design of Finite State Machine is experimented, and it's proved to be effective of using optimization methods, and a common optimizing method of Finite State Machine is brought.Finally, a conclusion of the thesis is presented, and some further prospects of the research are made.
Keywords/Search Tags:Digital Integrated Circuit, Low Power, Clock-gating, Dynamic Power
PDF Full Text Request
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