Physical Design Of High-performance Cortex-A55 CPU Module Based On TSMC 12nm Process

Back-end(Physical)design is the physical realization process of chip design and is essential in the entire design process.The continuous development of integrated circuits and the continuous advancement of manufacturing processes have brought chip performance advantages,but also caused physical design to face many challenges such as difficulty in timing closure,increased power consumption,routing congestion,signal integrity,and manufacturability issues.The back-end design has two main directions:low power consumption and high performance.At present,the research on low power consumption at home and abroad has gradually improved,but the system research on high performance is rarely involved.At the same time,as the core part of electronic information technology products,CPU is also the most strategically valuable product in the semiconductor industry,and its related design and development has great academic and practical significance.This thesis is derived from a TV project under the TSMC 12nm process of the internship company.The physical design and verification of the high-performance CPU module is completed,and finally the layout file with correct function,physical design rule meeting the TSMC 12nm manufacturing process rules,and time sequence meeting sign-off requirements is obtained.The main tasks of the thesis are as follows:(1)Based on the IC compiler II tool,the physical design of the block-level CPU module is realized,including floorplan,place,CTS(clock tree synthesis),and route.In Floorplan stage,block PD and TOP PD cooperate to plan the size and port location of the module,considering the data interaction with other modules,module interface timing,and implementation difficulty;based on data flow,routing resources,and physical design rule's constraints,the macro placement is completed;and realize the power supply connection.The Place stage studies the optimization strategy of PPA(performance,power consumption,area).Reordering the scan chain to optimize the routing resources,subdividing the timing path group to optimize the timing,and adopting the strategy of timing and congestion-driven placement and two-pass placement flow to complete the standard cell placement and optimization.At the same time,the solution to unreasonable logic distribution,poor timing situation and routing congestion is studied.The clock tree synthesis stage studies the selection rules of clock cell,the design of clock tree routing rules,the metrics of clock tree quality,the optimization strategy of clock latency and clock skew,and uses CCD flow to complete the construction and optimization of the clock tree.In the Route stage,the signal net routing and optimization are completed,and the repair strategy for design rule violations including short is studied at the same time.(2)Based on calibre DRC/LVS,complete the physical verification of the CPU module and the design of the repair strategy for physical rule violations,and combine the ICC II graphical interface to complete the physical rule repair,ensuring the manufacturability and functional correctness of the final realized CPU module layout under the TSMC 12nm process;based on prime time to complete the timing verification of the CPU module and the design of the repair strategy for timing violation,combined with ICC II for ECO to achieve timing repair,to ensure that the design timing meets the constraints,while studying the principles and repair strategies of common timing violations.(3)Complete the physical design of the quad-core 1.5GHz high-performance CPU module under TSMC 12nm process,achieve the design goal and meet the sign-off requirements.The final design PPA index is:the main frequency is 1.69GHz,the static power consumption is 195m W,the dynamic power consumption is 398m W,and the area is 3.71mm~2.The TV chip based on the CPU module designed in the thesis has been successfully taped out and put into production.The research in the thesis focusing on the work of each stage of the physical design process,the indicators of measuring performance,the strategies of optimizing performance,and the proposed solution of the key issues in physical design(including the macro placement,the analysis and repair of routing congestion,the inspection and optimization of clock tree quality,the repair of physical rule violation and timing violation,etc.)have a certain reference value for physical design of the similar high-performance modules.