Research And Implementation Of Pdcch Blind Detection Process For 5G Road Tester

5G is a digital communication system with large connection,low delay,wide coverage and high reliability.With the large-scale deployment of 5G around the world,communication test equipment has become a global research and development hotspot.It is the basis for testing the quality of 5G network,exploring new signals and scenarios,and verifying 5G equipment and solutions.This project is based on the major theme project of technological innovation and application development"R&D and application of 5G Road Tester"in Chongqing,to study and implement the blind detection process of 5G Physical Downlink Control Channel.According to the requirement of 5G system for higher parsing rate of DCI,an improved CCE validity blind detection algorithm is proposed.The first aggregation level is matched by SINR of the current period,and the subsequent aggregation levels are sorted and searched.The threshold condition is used to determine whether the candidate set of maximum energy CCEs within the current polymerization level meets the detection requirements.At the same aggregation level,the algorithm can perform DCI analysis on at most one CCEs candidate set.The simulation results show that the average detection times of the improved algorithm are reduced by 74.67%,68.97%and 28.80%,respectively,compared with the traditional poor search algorithm,CCE hard decision algorithm and power detection algorithm.The blind detection efficiency is improved,and the performance is more stable when the channel quality is better.The performance of polar code decoding is an important factor to determine the efficiency of PDCCH blind detection.Based on SSCL decoding algorithm,an adaptive SSCL decoding algorithm is proposed to de-redundancies the path selection process after code tree path splitting.Through Path Metric(PM)placeholder,sorting and decoding termination characteristics,the sorting complexity of PM is reduced and the time step boundary of SSCL decoding algorithm is shortened.The simulation results show that the improved algorithm reduces the time steps min(L-1,N _v)of R1 node and the time steps min(L-1,N _v)(10)1 of SPC node of SSCL algorithm,and improves the decoding efficiency without reducing the decoding performance.Based on the research of PDCCH blind detection process algorithm,the FPGA design and implementation of PDCCH blind test process are carried out by adopting the modular design idea.Blind detection control module,which is implemented by state machine,and the modules such as demodulation,deconstruction,solution rate matching and polar code decoding are implemented by serial and parallel pipeline.At the same time,through Model Sim simulation test,the correctness of the design scheme is verified.Finally,the system's resource occupation,time consumption and the whole machine integration test results are analyzed and verified.Relevant test results show that the design scheme adopted in this thesis realizes fast analysis of DCI,with the main resources occupying less than 10%,and the throughput rate of the system's upstream and downstream reaches 95%of the theoretical value,which meets the application requirements.