Research And Implementation Of Physical Downlink Control Channel In 5G Monitoring System

5G(5th-Generation)has become a new generation of international mainstream communication standards.The structure of 5G networks is more complex than traditional LTE(Long Term Evolution)networks,which gives network testing and maintenance huge challenge.In order to overcome the technical difficulties of 5G network end-to-end testing,a new generation of 5G monitoring system is proposed.In the 5G system,PDCCH(Physical Downlink Control Channel)is the core of resource scheduling.Therefore,it is an essential key for the normal operation of the 5G monitoring system to parse PDCCH quickly and accurately.Based on the 3GPP R15 version 5G protocol standard,this thesis research and implements the PDCCH channel in the 5G air interface monitoring system,researches the principles and algorithms of each module in the PDCCH reception processing flow,and completes the FPGA(Field Programmable Gate Array).The main work of this thesis is as follows:1.Analyzes the performance and complexity of the channel estimation algorithm and the SCL(Successive Cancellation List)algorithm of Polar decoding in the PDCCH.The scheme combining the least square method and linear interpolation is selected as the implementation scheme of the channel estimation module.The SCL decoding algorithm with a path width of 8 is selected as the implementation algorithm of the Polar decoder.2.Research the PDCCH blind detection scheme and proposes an improved blind detection scheme based on spectrum sensing.Under the simulation parameters set in this thesis,the average blind inspection times of the improved blind inspection scheme are much lower than the exhaustive blind inspection scheme and higher than the power detection blind inspection scheme,but the probability of missed detection is lower than the power detection blind inspection scheme.A blind inspection scheme with a relatively balanced blind inspection efficiency and blind inspection performance.In order to meet the real-time requirements of the current stage of the project,this thesis selects the power detection blind detection scheme with the least number of blind detections as the PDCCH blind detection scheme for this subject,and performs FPGA design and implementation.3.Use Verilog hardware description language to implement FPGA implementation of each module in the PDCCH receiving link and build a complete PDCCH receiving link.Use Model Sim simulation software to perform functional simulation on each module to verify its correctness.Finally,resource consumption analysis and timing analysis are performed on the overall link to verify the rationality of the design scheme.FPGA Simulation results show that:The design scheme of this thesis can accurately and quickly parse PDCCH.In 200 MHz system clock,the maximum time required for the system to complete a PDCCH reception processing flow is about 0.125 ms,which meets the time requirement for data processing in the protocol.The overall consumption rate of FPGA chip resources is about 9%,which provides conditions for multicellular and multichannel expansion.