Research On The Key Technologies And The Implementation Of The Multi-User PDCCH Channel Of TDD-LTE System

Long-Term Evolution(LTE) has been rapidly developed and widely used over the recent years. And Time Division Long Term Evolution(TDD-LTE) has become the main trend of LTE. This thesis studies the key technology and implementation of Physical Downlink Control Channel(PDCCH) of TDD-LTE system and implements PDCCH over the TMS320C6670 Multi-core DSP platform.This thesis studies the physical layer protocol of TDD-LTE and sorts out the formats and functions of PDCCH. Firstly, this thesis studies the key algorithm of transmitter and receiver. By algorithm selection, the basic flow of receiving and sending procedure is designed. Then this thesis constructs the link-level floating emulation platform on Matlab to study the performance of PDCCH with all the four different formats under Additive White Gaussian Noise(AWGN) Channel and Rayleigh Channel. Additionally, the effects of single antenna and transmit diversity on the performance of the channels are studied.This thesis studies the Serio Rapid I/O(SRIO) of TDD-LTE experimental system. This thesis analysizes the system specifications and programming mechanism of SRIO. According to the integral structure and protocols of the experimental prototype, this thesis designs a complete data transmission model for SRIO-based physical layer, MAC layer and radio frequency(RF) unit. The connectivity of SRIO between physical layer and MAC layer, physical layer and RF unit is tested. Then the paper tests the data transfer rate between DSP and MAC layer, DSP and RF unit, which proves that SRIO can satisfy the demand of data transmission of the testing system.This thesis studies the features of TMS320C6670 Multi-core DSP platform and implements a PDCCH transceiver under this platform. Bit Rate Coprocessor(BCP) is used in this transceiver to accelerate the CRC addition, rate matching, tail-biting convolutional coding and modulation procedures of the PDCCH transmitter.This thesis focuses on the implementation of blind detection process. Because of the lack of prior information, PDCCH has to blind detect on the receiver to resolve information. According to the protocols, the times of blind detection can reach up to 44, which makes it the performance bottleneck of the entire experimental system. This thesis compares two alternative accelerating schemes for decoding module, which are method based on software optimization and method based on Viterbi-Decoder Coprocessor 2(VCP2) respectively. By joint use of inline instructions and Enhanced Direct Memory Access3(EDMA3), the blind detection efficiency is enhanced. Test results show that the system can complete the task within the specified time even under the worst situation with 44 times of blind detection.Through the analysis of different calibration modes, this thesis verifies the validity of the calibration selection of the testing system. This thesis tests and analysizes the performance of soft decoding and hard decoding methods, and chooses soft decoding method as the decoding method for the testing system based on its advantage of performance. This thesis tests the DSP-based PDCCH transceiver through channel emulator and analyzes the performance of this system under AWGN Channel. The correctness and validity of the link is verified through the comparison with Matlab floating-point simulation results.At last, this thesis makes a conclusion for the entire research, and indicates the future research directions.