| The Long Term Evolution-Advanced(LTE-A)system has been the mainstream communication standard in the world,the national security departments need to use the third party instrument to lawfully monitor some users in the interests of national security,so it’s necessary to design the third party monitoring instrument in the communication standard of LTE-A system.Based on the project requirement of “FPGA and DSP software of LTE-A downlink signal processing” in a Research Institute of the General Staff,Physical Downlink Control Channel(PDCCH)of LTE-A monitoring system is researched and implemented.PDCCH is not only the core of resource allocation and scheduling in the whole LTE-A monitoring system,but also plays the role of connecting,the third party instrument quickly and correctly parse PDCCH,which is the primary prerequisite for obtaining the business information of the monitored users.Based on the processing procedure of PDCCH transmitter,this thesis focuses on the procedure of the third party instrument getting the Identify(ID)of monitored users and the basic principle of each module of PDCCH recciving link.Basides,the Field Programmable Gate Array(FPGA)design scheme of each module is given,and it is realized in the procedure of obtaining the ID of monitored users.In the research of PDCCH blind detection process,not only analyzes the traditional exhaustive blind detection algorithm and correlation blind detection algorithm,but also studies the power allocation of PDCCH resource unit and presents a power allocation blind detection algorithm to resove the shortcoming of the two kinds of algorithm.Compared with the traditional exhaustive blind detection algorithm and the correlation blind detection algorithm,the power allocation blind detection algorithm reduces the maximum number of blind detection from 44 times and 32 times to 12 times.Thus,the efficiency of blind detection is improved.The simulation results show that when the SNR is greater than 5dB,the average number of the power allocation blind detection algorithm is much lower than the traditional blind detection algorithm.Balancing between algorithm performance and the number of blind detections,and considering the requirement of the project,the correlation blind detection algorithm is selected to implement the FPGA scheme.According to the design of each module,the PDCCH receiving link is implemented by FPGA,and the detailed analysis of each module,the Modelsim function simulation and the Chipscope online logic timing diagram are given.Finally,the FPGA resources and time consumption of the whole PDCCH receiving link are analyzed,which proves the correctness of the design.The design has been applied to the actual project,which has a certain reference significance to the development of other relevant system and pre-research project in the future. |
