The Implementation Of The Downlink PDCCH Blind Detection Based On FPGA

In order to integrate the mobile communication with the broadband wireless access better,3GPP initiated the development of this project-LTE (Long Term Evolution). The LTE system improves and enhances the air interface technology in3G, using orthogonal frequency division multiplexing (OFDM) and multiple-input multiple-output (MIMO) as its basic technology of evolution, which can provide higher transmission rates, optimize packet data applications, obtain low delay and increase the capacity and coverage, etc.. Moreover, LTE and its enhanced version, LTE-Advanced, is becoming a new generation mobile communications standard, after the third generation.Physical Downlink Control Channel (PDCCH) plays a crucial role in the scheduling of LTE system, which assigns a variety of resources to the uplink and downlink transmission. A PDCCH carries a message known as Downlink Control Information (DCI), one of the most important control information in the LTE physical layer, which includes a group of UEs for the scheduling information in downlink and uplink data transmission and the uplink power control information. In order to use the resources of control area effectively, and reduce the signaling cost of PDCCH, a blind detection method is used to obtain the downlink control information. Each PDCCH supports multiple DCI formats and resource locations occupied by the DCI format, which is priori and unknown to the terminal (UE receiver). Then the terminal tries to demodulate and decode all possible DCI formats and resources locations, and obtain their own information by blind detection.Based on the further research in the agreements, standard or proposal related to LTE, this paper realized and verified the method on FPGA platform with Verilog HDL language.A PDCCH Blind Detection method designed in UE receiver, with LTE standard as the main and theoretical basis, which is of great significance for the terminal (UE receiver) of the LTE system design. What’s more, the method proposed in this thesis has a hardware feasibility and important reference value for the relevant system development and pre-research project in the future.