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Study On Error Analysis And Correction Method Of Ultra-high Speed Parallel Sampling System

Posted on:2022-05-09Degree:MasterType:Thesis
Country:ChinaCandidate:W XuFull Text:PDF
GTID:2518306572995869Subject:Mechanical engineering
Abstract/Summary:PDF Full Text Request
The measurement of weak electrical signal needs higher signal conversion speed and sampling accuracy,so it puts forward higher requirements for the speed and accuracy of the sampling system.In the case of limited chip performance and process in the market,to design a sampling system with a sampling rate of 20 GHz,a multi-channel ADC board level parallel sampling method based on time alternation can be adopted.When the system is sampling in parallel,the mismatch error will be caused by the inconsistency between channels.In order to ensure the sampling performance of the system,it is necessary to study the mismatch error correction method.The specific research contents of this paper are as follows:First of all,according to the requirements of the sampling system,combined with the existing conditions,the ultra-high speed parallel sampling system is established in the way of time alternation,and the theoretical derivation and verification are carried out;based on the system implementation method,the selection of key devices and the design of multichannel clock are completed,and the overall hardware block diagram of the ultra-high speed parallel sampling system is built,which provides reference for the hardware implementation of the parallel sampling system For reference.Secondly,starting from the source of mismatch error,the time and frequency domain characteristics of mismatch error in parallel sampling system are analyzed,the influence mechanism of mismatch error on system performance is clarified,and the mathematical modeling of mismatch error is completed;the mismatch error model of parallel sampling system is established in MATLAB,and the error simulation analysis of three kinds of mismatch is carried out;the dynamic performance evaluation method of parallel sampling system is proposed,The dynamic performance of the system under the influence of mismatch error is analyzed.According to the ADC chip selected in the hardware implementation,the limit value of the system mismatch error is calculated,and the correction performance of the algorithm is measured by the following.Then,the mismatch error correction algorithm is deeply studied,and the reference system correction algorithm and the statistical correction algorithm are proposed.The former needs to set up additional parallel reference channels to obtain the mismatch error information between channels,while the latter mainly uses the statistical law of the sampled data to estimate the mismatch error difference.The two algorithms are simulated and verified by the mismatch error model of the parallel sampling system,the dynamic performance of the system after the algorithm correction is compared and analyzed,and the statistical correction algorithm is determined as the system correction scheme.Finally,the ADC evaluation board is used to build a two channel parallel sampling system platform,and the platform is used to complete the comparative test of the correction algorithm to verify the practicability of the system error correction scheme.
Keywords/Search Tags:Time alternating, parallel sampling, System Scheme Design, Mismatch error model, Error correction algorithm
PDF Full Text Request
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