Tiadc Time Error Correction And Waveform Interpolation Algorithm In The System Hardware Design And Implementation

In order to meet the needs of the modern time-domain test, quickly and accurately capturing complex and broa d-band signal, test instruments require higher real-time sampling rate. The main method to improve real-time sampling rate is multi-chip ADC time-interleaved parallel sampling technology. However, the back-end digital signal real-time processing meet challenges for large-scale parallel sampling.Data real-time processing in Digital Signal Processor is the traditional method, but the processing ability of the DSP processor can not meet the requirement of the high-performance instruments. FPGA parallel processing mechanism can greatly upgrade the data processing speed. To improve the instantaneity of data processing, this dissertation will research the FPGA realization of digital signal processing algorithms. The realization of digital signal processing algorithms in hardware system is becoming the current research focus. Combined with projects in master’s study period, the dissertation mainly does some thorough research on the following aspects in the digital storage oscilloscope:(1) The first part of this dissertation is to study the design and realization of time non-uniform error correction algorithms of time-interleaved parallel sampling system in hardware. The dissertation designed time non-uniform error correction algorithm based on Matlab, devised FPGA hardware architecture of the time correction algorithm, and completed all code development and logic function simulation. Simulation, debugging and analysis results show that the algorithm is correct and the hardware implementation is feasible.(2) The second part of this dissertation is the hardware design and implementation of the50times interpolation algorithm. The dissertation chose interpolation filter structure based on50times interpolation algorithm of UT2000M digital storage oscilloscope. The software tested the processing time of50times interpolation algorithm in the DSP processor or in the FPGA. Test results show that the hardware can greatly upgrade the processing speed and greatly help to improve the whole system performance. The results of actual debugging show that the hardware implementation of digital filtering algorithms can greatly improve the system instantaneity.