Research On Error Correction Of TIS System Based On FPGA

In recent decades,with the development of signal processing,automotive electronics,military radar,software radio and other fields,people's requirements for Analog-to-Digital Converters(ADC)are getting further high,which mainly reflects in the two design indicators of high sampling speed and high resolution of ADC.In the actual design,the high speed and high resolution of ADC are often exist as mutual constraints,so that the performance of high processing speed and high resolution cannot be achieved simultaneously,however the proposal of Time-Interleaved Analog-to-Digital Converter(TIADC)precisely solves this problem.The Time-interleaved Sampling(TIS)system realized by the combination of multiple low-speed analog-to-digital conversion chips can well meet people's requirements for high conversion speed and high resolution.The proposal of the TIS system provides a new direction for the high-speed analog-to-digital conversion system,and brings a large number of researchers who have begun to conduct in-depth research.In the actual system construction and application process,further research found that due to the limitations of the manufacturing process level,there are a large number of channel mismatches in the TIS system,which can be roughly divided into three categories,including DC offset mismatch,gain mismatch,sampling clock skew mismatch.If these channel mismatches are not corrected,the mismatch errors generated by channel mismatches will directly affect the system,even seriously affect the system performance and also reducing the overall system index.Looking at the current research situation at home and abroad,the technical level of domestic realization of high-speed TIS system differs greatly from that of foreign countries.Due to the fact that the start of domestic research are relatively late and the theoretical achievements are relatively few,the need for channel mismatch correction technology for TIS systems has become particularly urgent.Combining the features of Field Programmable Gate Array(FPGA),which has strong programmability,fast processing speed,and high control flexibility,this paper conducts an in-depth research on the error correction technology of TIS system based on FPGA,focusing on the use of full digital background method realizes the correction of the channel mismatch error of the TIS system.The work of this paper is as follows:1)The working principle of the TIS system is introduced in detail,the various errors that will occur in the actual system working process are analyzed,and the TIADC full-band DC,gain,and sampling clock skew mismatch error correction method based on first-order statistics is introduced.On this basis,the autocorrelation-based clock skew mismatch estimator and the second-order Taylor-based sampling clock skew mismatch correction structure are further deduced.2)The core modules of the TIS error correction system are designed and implemented in FPGA,including DC offset error correction module,gain error correction module,and sampling clock skew module.The principle of the Finite Impulse Response(FIR)digital filter is analyzed in conjunction with theoretical research,and a filter implementation scheme suitable for this TIS error correction system is selected by analyzing existing filter FPGA implementation structure.On the basis of optimization and improvement,a full-speed polyphase filter structure suitable for high-speed TIS error correction system is proposed.3)Complete systematic joint debugging and analysis,test and analyze the function,timing and performance of each module,and optimize and improve each module to varying degrees,and improve the overall operating speed of the system on the basis of saving system hardware resources.Based on the above research foundation and core module design,the 14bit-25.6GHz8-channel TIS error correction system was built through systematic debugging and assembly,and finally the system performance and index tests were completed in combination with MATLAB,which verified the feasibility and optimality of the system.