Error Correction Technology Of 12-bit 10GSPS Time Alternate Acquisition System

In the information age,with the rapid development of electronic information technology,higher requirements are placed on electronic measuring instruments.Therefore,time-interleaved ADC(TIADC)is the mainstream solution to improve the sampling rate in China.The prerequisite for increasing the sampling rate in the TIADC system is to realize the synchronization of multiple ADCs in the system.The higher the system sampling rate,the higher the requirements for synchronization accuracy.At the same time,the mismatch error caused by the inconsistency of multiple discrete ADC devices in the TIADC system will degrade system performance.This article mainly studies the acquisition synchronization of multiple ADCs in the TIADC sampling system,the improvement of system resolution under over-sampling conditions and the correction technology of system mismatch errors.According to the above three research contents,The specific research work of this paper mainly include:1.Based on the deterministic delay of the JESD204 B protocol and the synchronization reset of multiple acquisition boards,the synchronization of data acquisition,transmission and storage is realized.In-depth study of system synchronization and parameter setting and adjustment in synchronization control,the design system uses the deterministic delay of subclass 1 devices to achieve simultaneous sampling of multiple ADCs to achieve a 10 GSPS sampling rate,and uses multi-level clock devices and multi-level confirmation mechanisms to achieve multiple channels Synchronization of acquisition,transmission and storage.2.Based on oversampling,a system resolution improvement scheme is proposed.The simple and easy-to-implement average filtering and extraction scheme of the digital terminal is used to reduce the influence of noise on the system under the condition of system oversampling,and improve the signal-to-noise ratio of the acquisition system,thereby improving the resolution.3.Based on the TIADC error model,an error correction scheme combining coarse sinusoidal fitting correction and frequency response mismatch error correction is proposed.In-depth research on the source of the mismatch error in the time alternating system,using the sinusoidal fitting error estimation algorithm and the analog correction scheme to realize the rough correction of the mismatch error;on the basis of the rough correction,the reconstruction filter bank is used to realize the frequency response mismatch error reconstruction and correction of errors,focusing on the research of the amplitude-frequency compensation FIR filter in the reconstruction filter bank,the principle of the phase-frequency reconstruction all-pass IIR filter and the fractional delay FIR filter and the FPGA implementation of the digital filter.The design of this paper is based on the 12 bit digital storage oscilloscope platform.Through the debugging of the analog end,the digital end and the upper computer software end,the four-channel 10 GSPS sampling rate multi-ADC synchronization and the resolution are increased to 14 bit.The error correction system makes the signal-to-noise ratio of the acquisition system within the 2GHz bandwidth reach 45 dB.