| CAN bus is one of the most widely used fieldbuses in the world.It is the de facto standard of vehicle-mounted bus because of its outstanding advantages such as high reliability,high realtime performance and high cost performance.The emergence of CAN FD solves the problem of load rate of CAN bus and reduces the cost and risk of network update.Due to the long cycle of vehicle renewal,CAN and CAN FD will appear in the vehicle network for a long time.Therefore,it is necessary to study the controller compatible with the above two protocols.This paper refers to the existing CAN bus controller architecture and CAN FD protocol specification,and designs a controller compatible with CAN/CAN FD protocol,which is mainly composed of nine functional modules.In order to realize the compatibility of the two,the protocol state machine in the control module dissolves different message structures and divides them into different states,and realizes the related receiving and sending functions of CAN and CAN FD by state jump.Two CRC check algorithms CRC17 and CRC21 are added to check the error of CAN FD messages with different data lengths and different standards.The bit coding module is not only responsible for the bit filling of CAN message,but also responsible for the fixed filling operation in the corresponding bit field of ISO CAN FD.In order to realize the variable rate of CAN FD message transmission process,two sets of time unit generation modules are configured in the frequency divider to achieve the purpose of rewriting the nominal rate and data rate through the configuration of time unit number and bit timing sequence.In this paper,the realization mode,data path and state jump of each module are described in detail,and the related functions stipulated in the protocol are realized.Simulation results show that the functions of the designed controller are correct.The FPGA comprehensive report shows that 5714 LUT logic units,70 LUTRAM,3309 FF and 5 BRAM are used,and the working frequency can reach up to 93MHz.The protocol controller implemented by FPGA can communicate with commercial nodes normally.It shows that the designed controller index meets the design requirements.HHGRACE 0.11 μm process layout was used to design parallel flow plates.This design can provide a reference for the same type of controller and has a good development prospect and practical value. |
