FPGA Implementation Of Rate-compatible QC-LDPC Codec Based On IEEE802.16e Standard

Low-density parity-check(LDPC) codes, as an excellent Channel Error Correction Codes, have become the most notable hotspot and widely used in various communication standards, such as IEEE802.16 e, IEEE802.11 n, DVB-S2 and CMMB standards. In order to support multiple business needs and improve the adaptability of the requirements, most communication standards require LDPC codes support flexible coding length and rate.The implementation of codec on which 1008 length 1/2 rate and 1024 length 3/4 rate are compatible very well,is based on the actual needs of the project. Resource consumption will be significantly reduced through effective storage strategy and the unique combination of QC-LDPC codes structure which is recommended by IEEE802.16 e standard, which achieves a balance between performance and latency, etc. This paper shows the main work around the implementation on FPGA to meet the requirements of one set of rate-compatible LDPC codec based on IEEE802.16 e standard.This paper briefly introduces the basic theory of LDPC codes and QC-LDPC codes. After derived various algorithms systematically, including traditional encoding algorithm, RU encoding algorithm, QC-LDPC linear encoding algorithm and BP algorithm, min-sum algorithm, normalized min-sum algorithm, etc. This paper compares their performances and implement costs, and then determines the most suitable QC-LDPC encoding algorithm and normalized Min-sum decoding algorithm for hardware implementation.With the help of simulation software and detailed discussion, this paper determines the FPGA implementation quantization scheme where the soft input information 4bit quantified, intermediate data 12 bit signed integer represented. Combined with the quasi-cyclic double diagonal structural characteristics of QC-LDPC in IEEE802.16 e standard, rate-compatible semi-parallel data processing hardware structure and storage strategy based on location addressing are designed. The overall design method of using pipelines and ping-pong operations, can effectively improve the delay characteristics of the codec.Finally, the paper focuses on the implementation of rate-compatible QC-LDPC codec. Using the hardware description language in Quartus II software platform, the paper implements the design of codec. The simulation results indicate that the codec hardware architecture and storage strategy can meet the design demand.