Design Of A 11-bit Columnparallel Cyclic ADC For Monolithic Active Pixel Sensor

The monolithic active pixel sensor(MAPS)based on the CMOS VLSI process,with its advantages of low power consumption and low cost,is widely used in the most advanced high-energy physics experiments in the world,as the vertex detector for particle tracking.In a high-luminosity experiment,a large number of particles will be generated at the intersection of the particle beam in a very short time.Particles will scatter in multiple levels in the detector layer to form multiple related vertices,which overlap in space,making it difficult for the detector to distinguish the true vertices.By detecting the time and energy information of the particles,the collision event of each particle can be correctly reconstructed.In the case of a high particle rate,stricter requirements are imposed on the readout rate of the detector.The use of an off-chip analog-to-digital converter(ADC)to digitize the analog output will limit the readout rate of the entire system.In order to meet the requirements of future high-energy physics experiments for pixel detectors,the pixel detector adopts a scheme of integrating column-level ADCs inside the array to achieve a higher readout rate.After investigating the column-level ADC used in the pixel detector,the characteristics of various structures are analyzed and compared.Considering the requirements of power consumption,layout size and converion rate,a Cyclic ADC with a readout rate of 4MS/s and an accuracy of 11 bit is designed.The ADC in this paper adopts the SHA-less architecture,which reduces a sampleand-hold period compared to the traditional structure.Each cycle adopts 1.5bit redundancy algorithm and a switched capacitor sub-ADC is designed based on the input offset storage technology,which can effectively reduce the offse of comparator.Based on the capacitor multiplexing technology,a MDAC circuit which converts twice in a single clk cycle and is conducive to low-power design of Cyclic ADC,is also proposed.The proposed ADC is designed and fabricated in GSMC 130-nm CMOS technology,which has a power consumption of 3.33 m W,a layout area size of 60?m×670?m,and an ENOB greater than 10 bit,and achieves the Fo M of 0.47 p J/conv.-step.This design has certain advantages in terms of low power consumption.The accuracy,speed and layout size of ADC show that this design suitable for column-parallel readout circuit in MAPS.