Research And Implementation Of Low-noise Front-end Electronics Of Monolithic Active Pixel Sensors For ALICE ITS

Monolithic Active Pixel Sensors (MAPS) will equip the new ALICE (A Large Ion Collider Experiment) Inner Tracking System (ITS) at CERN during the second long shutdown of the LHC in 2019. For the discrimination system, the noise not only affects the resolution of the energy measurement, but also determines the minimum threshold detected, affecting the detection efficiency. Therefore low noise is a primary requirement for the ALICE ITS upgrade. MAPS receive interest for the ITS upgrade as they integrate the sensor and readout electronics in one silicon die with potential for low sensing node capacitance, low material budget and cost, and easy assembly. A low sensing node capacitance or a low feedback capacitance allows for a reduction of the Equivalent Noise Charge (ENC) for a given power consumption and bandwidth. Hence four methods to reduce the noise of front-end circuits are proposed:1). a novel source-drain follower where both the source and drain follow its gate potential is proposed for charge readout.2). A method to implement a small feedback capacitance by two routing metals is proposed. The distance and area of the capacitance are increased to reduce its mismatch. The structure of the capacitance is also modified to reduce the capacitance mismatch.3). Detailed Monte Carlo simulations have been done to reduce each transistor mismatch contribution to the pixel-to-pixel charge threshold dispersion.4). A cascode transistor has been added to reduce the impact of variation of the parasitic capacitance on the pixel-to-pixel charge threshold dispersion.The research contents and innovation points in this thesis are discussed in the following.1. A novel source-drain follower is proposed. Source followers are widely used for MAPS readout: they increase charge-to-voltage conversion gain 1/Ceff or decrease the effective sensing node capacitance Ceff because the follower action compensates part of the input transistor contribution to the effective sensing node capacitance. A novel source-drain follower compensates both the gate-source and gate-drain capacitance thus it potential further improves the charge-to-voltage conversion gain and reduces the ENC. The DC voltage gain of the novel source-drain follower is closer to unity than the one of the conventional source follower. Both novel source-drain followers and conventional source followers have been implemented in the INVESTIGATOR detector to compare their performance. It is also to study to reduce the sensing node capacitance by increasing the substrate back bias. The INVESTIGATOR detector has been tested using 55Fe radiation source. Increasing the substrate back bias from 0 V to -6 V, the sensing node capacitance is reduced by 49% from 5.96 fF to 3.04 fF and ENC by 36% from 80 e- to 51 e. Compared to the conventional source follower, the novel source-drain follower reduces the sensing node capacitance by 9% from 3.04 fF to 2.76 fF and ENC by 25% from 51 e- to 38 e-.2. A method to reduce the feedback capacitance by two routing metal parasitic capacitance is proposed. A low feedback capacitance allows for a high charge-to-voltage conversion gain for a Charge Sensitive Amplifier (CSA). Two ways to reduce the mismatch of the parasitic capacitance between two routing metals are introduced. One is to increase the distance and area using two non-adjacent routing metals. The other is that the structure of the capacitance is modified to reduce the edge effect on the capacitance variation. A parasitic capacitance of 0.2 fF between metal2 and metal4 by this method is implemented in the pA_LP detector. Hence a large charge-to-voltage conversion gain is obtained and the ENC is reduced. From simulations, the CSA has a noise of 18 e- at a peaking time of 300 ns and the power consumption per pixel is only 45 nW.3. Monte Carlo simulations have been done to reduce the transistor contribution to the pixel-to-pixel charge threshold dispersion with a constraint of small area. This method is proposed to optimize the pixel-to-pixel charge threshold dispersion of the front-end circuit in the ALPIDE detector. The front-end circuit in ALPIDE is composed of an amplifier and a current comparator. Detailed Monte Carlo simulations have been done to estimate each transistor mismatch contribution to the pixel-to-pixel charge threshold dispersion. The transistor sizes have been scaled to optimize the pixel-to-pixel charge threshold dispersion caused by the transistor devices mismatch with a constraint to fit the front-end circuit in the area of 220 ?m2. From simulations the pixel-to-pixel charge threshold dispersion caused by the transistor device mismatch has been reduced by 67% from 6.10 e- down to 1.99 e-. The temporal noise has also been reduced by 9% from 3.70 e- to 3.37 e-. The analogue power consumption is only 40 nW.4. A cascode transistor has been added to reduce the gate-to-drain voltage gain of the input transistor thus reducing the equivalent miller's capacitance. This method is also proposed to optimize the pixel-to-pixel charge threshold dispersion of the front-end circuit in ALPIDE. A cascode transistor has been added in the second-stage current comparator to reduce the impact of the input transistor gate-drain parasitic capacitance mismatch on the pixel-to-pixel charge threshold dispersion. From simulations the pixel-to-pixel charge threshold dispersion caused by the parasitic capacitance variation of the second-stage input transistor is reduced by 73% from 2.19 e-/0.1 fF to 0.59 e-/0.1 fF. The optimized front-end circuit has been implemented in ALPIDE. The ALPIDE detector will be equipped in the new ALICE ITS in 2019.