Design And Verification Of TLB

Paged memory management technology have been used extensively in microprocessor designs, but its realization needs not only software support but also hardware support. TLB (translation look-aside buffer) is one of the supporting components, which is a logic subsystem used to speed up the translation of address.TLB is mainly composed of CAM and SRAM.CAM is the core unit,which is in charge of comparison of the linear address.the result of the comparison is the key to make TLB functional.so,CAM arrays has been an important functional component in TLB which can highly improve on the performance of microprocessor.The other function module is SRAM.in this paper,the logic structure of SRAM unit is little different from the ordinary SRAM in X microprocessor.we will find that the output control is integrated in SRAM,not like the others,which is integrated in the output circuit.On the basis of deep research on TLB technology, this paper presents the logical circuits and layout design of the TLB module in the data Cache of the X microprocessor. According to the system design requirement, it makes sure that the X microprocessor can get the address translated from the TLB in one cycle when hit. On the system verification platform, the simulation in system level about TLB is taken, and the results conform to the original intension of our design. Simultaneously, deeply SPICE simulation on the entire TLB design is applied, and we focus on the simulation and analysis of the hit judgment circuit.meantime,we also introduce some registers about TLB,such as test register and control register.which help us to get a better understand of TLB.