Design Of Memory Management Unit In 32-bit MIPS Processor

With the rapid development of China's electronic information industry,the independent research and development of general-purpose processor(GPP)is imminent.the past thirty years,the microprocessor's operating frequency continues to increase rapidly,but the development of memory is lagging behind compared to the rapid development of microprocessor performance,which greatly lower the work efficiency of the microprocessor.At present,most microprocessors use hierarchical storage systems and memory management unit which were tightly coupled component,to enhance the storage system access speed.The memory management unit(MMU),as one of the core technologies of the genera-purpose processor,is critical to its operational efficiency.Therefore,the study of memory management unit design has great academic value and practical significance.This paper develops the design objectives of MMU in a 32-bit MIPS processor based on deeply studying the functional characteristics of virtual memory system and memory management unit(MMU)and making the requirement analysis.This study also completes the micro-architecture design of the MMU and then separates the functional module.In addition,on the basis of Verilog hardware description language,this paper has a detailed design to MMU register group,MMU control module,instruction translation look-aside buffer(ITLB)module and data translation look-aside buffer(DTLB)module.The MMU can translate the virtual address to the physical address and provide protection to memory permissions under two modes: user mode and supervisor mode.Among them,ITLB and DTLB modules both adopt direct mapping structure,with 64 entries of the capacity,and they are used as translation to the instruction address and data address.In order to save memory space,the design puts to use hierarchical page table(PT)structure.In the design process of page table entry(PTE),the system could set the corresponding enable status for different work mode,and process ID to protect the memory space.The writer establishes a verification platform,which is divided into three parts,namely the system task to generate the virtual address,read and write registers,and initial system and so on,the MMU RTL model and the excitation and response.According to the test plan,the writer could develop the test case and apply the excitation in the platform to get the response,confirming whether the response meets the expected functional objectives,until all the functions of MMU can be achieved correctly.The simulation results from the verification platform show that the MMU can perform the translation of virtual address(VA)to physical address(PA)and provide memory protection.The simulation results of FPGA manifest that the maximum operating frequency of MMU has reached 165 MHz,and the resources occupation rate of LUT is less than 13%.Therefore,the MMU performs well and it meets the design requirements in this study.