Research On Key Components Of Frequency Fynthesizer For 5G MmW Applications

As mobile communication enters the 5G era,the frequency spectrum of the sub-6G frequency band has been very crowded,and it is difficult to meet the increasing demand for communication speed and capacity.Therefore,the millimeter wave communication technology that can provide a larger bandwidth has attracted widespread attention.The phase-locked loop frequency synthesizer is regarded as the heart of the radio frequency communication system and provides the local oscillator or clock signal for the system.For 5G millimeter wave applications,the development of a phase-locked loop frequency synthesizer with a wide frequency tuning range and low phase noise still faces many challenges.In recent years,siliconbased integrated circuit technology has developed rapidly,and has gradually become one of the mainstream technologies for the development of millimeter-wave radio frequency integrated circuits due to its high integration,high reliability,and low cost advantages.Therefore,this topic mainly focuses on the key modules in the high-performance CMOS frequency synthesizer based on CMOS technology.This article first introduces the cheoretical basis of the phase-locked loop frequency synthesizer,and then respectively introduces working principle design fundamentals of the frequency reference source in the charge pump phase-locked loop,the frequency detector,the charge pump the voltage-controlled oscillator and simulation.With the development of wireless communication technology,the trend of miniaturization of frequency reference sources is becoming more and more obvious,and reference crystal oscillators will also be replaced.This topic is based on high-Q thin film bulk resonator filters(FBAR),designed in TSMC 65 nm CMOS process an oscillator chip based on a cross-coupling structure is presented.The test results show that the oscillator works at 2.52 GHz and the phase noise is-134.5d Bc/Hz@1MHz.After three cascaded TSPC structure two frequency dividers divide by eight,it can be used as a reference source for frequency synthesizers.This thesis studies and designs an 8GHz voltage-controlled oscillator based on TSMC 65 nm CMOS process.In order to avoid complicated harmonic tuning,a Class-F234 voltage controlled oscillator is proposed.The principle is to increase the third harmonic impedance by introducing2,4 even harmonics without deteriorating its performance;introducing harmonics reduces the sensitivity of the oscillator to noise,so it can effectively improve the phase noise in the flicker and noise area performance.At the same time,the harmonic inductance coupling design can effectively reduce the chip area without reducing its performance.The core area of the chip is550×635um2,and it consumes 19.32 m W of DC power consumption under 1.2V supply voltage.According to post-layout layout electromagnetic simulation,the frequency tuning range is 6.42-9.69 GHz,and the relative bandwidth reaches 38%;for the 6.43 GHz signal,the phase noise at the 1-MHz frequency offset is-123 d Bc/Hz.In this subject,a phase/frequency detector and a charge pump circuit chip are designed.In order to expand the phase detection range of the PFD,the main delay that affects the phase detection range is obtained through a time sequence analysis method.In this paper,CP is designed to make its output voltage range wide,small jitter,and small current mismatch by adding dynamic feedback matching at the output.The logic of the PFD and CP cascade circuit is correct and the performance is good.Under 1V supply voltage,the current mismatch in the output voltage range of 0.1-0.8V is less than 2%.