The Accelerated Implementation Of SIFT Image Matching Algorithm On FPGA

Digital image is a major invention in the history of human science and technology,and how to automate digital image matching by computer has been a hot research problem in academia.The image matching algorithm based on SIFT feature extraction has strong robustness to changes in illumination,rotation,scale,viewing angle,contrast and noise level,and has become one of the best performance image matching methods once proposed,which has received wide attention from researchers.The main drawback of SIFT algorithm is that it has more computational steps and higher time complexity of computation,which makes it difficult to run in real time on embedded devices.To address this problem,this paper analyzes the SIFT algorithm and implements a real-time acceleration of the SIFT algorithm using FPGA parallel pipeline processing.Compared with similar FPGA acceleration solutions,the optimization work in this paper on the algorithm principle and algorithm implementation is described as follows:This paper addresses the problem of insufficient number of feature points caused by the scale space deletion of the SIFT algorithm in similar implementation solutions,and designs three groups of 15 layers of full-size scale space and five sizes of filter kernels,which makes the number of feature points detected in this paper increase by at least 15.39% compared with other solutions;in response to the problem of decreasing matching accuracy due to the use of fixedpoint numbers in similar solutions,this paper uses data in single-precision floating-point format for operations and replaces the fixed-point rotation implementation of the Cordic algorithm in similar solutions by designing a single-precision floating-point pipeline implementation of Taylor expansion,thus reducing the average error of the hardware implementation result of descriptor extraction to 0.136‰;in this paper,the Euclidean metric used in the matching part of the algorithm is replaced by zero-mean normalized correlation,which makes the average matching rate of features improve by 2.793% compared with the original SIFT algorithm,and the matching speed is not reduced by the full parallel pipeline implementation;to address the contradiction between the demand of logic resources and the limited resources on the board,this paper designs a parallel pipeline of cyclic cascaded filter cores,instantiates 5 filter cores,generates 15 levels of scale space,reduces the scale of implementation,and reduces overall resource consumption by 66.67%;by designing a pulsating array separation Gaussian filter parallel pipeline,the Gaussian filter separation is realized and the DSP resource consumption is further reduced by 90.99%.The hardware implementation platform deployed for the algorithm in this paper is Xilinx xc7vx690tffg1157-2,and the accuracy simulation and verification experiments of the algorithm are conducted using Matlab software.The experimental results show that the detection time of each feature point in this paper is 1.78 us at 150 Mhz clock,and the real-time frame rate can reach 374.53 fps for the input image with the resolution of 368×448.