Design And Optimization Of SIFT Algorithm For Image Matching

At present,with the development of artificial intelligence and computer vision,the field of image information processing has attracted much attention.Scale Invariant Feature Transform(SIFT),as the origin and representative of the new feature extraction algorithm,has been widely used in image feature detection and matching.With the increase of data size in geometry,the requirement of computing speed for SIFT algorithm becomes higher and higher,which makes SIFT hardware acceleration circuit more and more important.Therefore,this thesis mainly studies the optimization design of SIFT algorithm and its hardware acceleration circuit,so as to to achieve high throughput SIFT circuit and accelerate the speed of image feature detection and matching.Firstly,the influence of the size of convolution kernel and filtering approach on the response and repeatability of SIFT algorithm is analyzed.The 7×7 Gaussian kernel and direct filtering approach are determined to construct Gaussian scale space,which reduces the complexity of SIFT algorithm.According to the improved SIFT algorithm,an optimized pipeline parallel processing structure is designed in this thesis.Pixel-based pipeline operation is used for real-time detection of SIFT feature and extraction of SIFT descriptors.The circuit is mainly divided into six modules: Gaussian scale space construction module,Difference of Gaussian scale space extrema detection and contrast checking module,edge response rejection module,gradient magnitude and orientation calculation module,descriptor calculation module,normalization module.In order to improve computing speed and reduce hardware resource consumption,the edge response rejection module and normalization module are optimized.For the edge response rejection module,the second moment matrix is used not only to reject the feature of image edge,but also determine the main direction of the feature according to the generated eigenvectors with larger eigenvalues.The matching rate of image matching is improved,as well as the computational complexity of the algorithm and the occupancy of hardware resources are reduced through this method.For normalization module,multiplier and shifter are used to replace a large number of dividers in the module,which improves the computational efficiency and saves a lot of hardware resources.The experimental platform of this thesis is based on the Artix-7 series of XC7A200T-1SBG484 C FPGA,which is simulated and validated by the tools of Vivado and Matlab.The experimental results show that the SIFT circuit designed in this thesis can achieve 85% matching accuracy in image matching,and the SIFT feature descriptor can be extracted within each clock cycle(i.e.17.9 ns)at the maximum clock frequency of 55.9 MHz,and the SIFT feature detection time is 5.55 ms.The frame rate of the circuit is up to 175 fps when processing 640×480 images.