SIFT-Based Feature Extraction Hardware Accelerator For Image Matching Application

Image matching is a fundamental process of many computer vision applications,including image stitching,object or scene recognition,visual localization and so on.Among feature extraction algorithms for image matching,Scale Invariant Feature Transform(SIFT)is one of the most famous ones,due to its robustness.However,SIFT suffers from high computational complexity and great amount of computation resource consumption.It's a challenge to design a real-time hardware accelerated Scale Invariant Feature detector.In this paper,we propose a real-time FPGA hardware accelerated architecture of SIFT algorithm.The architecture consists of two main components: the key-point detection(KPD)component and the feature generation(FG)component.To enable loose coupling,the two component work at different frequency and are connected with asynchronous buffers.In this way,quasi-parallelism is achieved between the two components.The KPD component adopts an octave-interleaved scale-parallel pipeline structure,as a tradeoff between frame rate and resource consumption.The FG component works in task-level burst mode for each key-point.Similarly,task-level quasi-parallelism is enabled between main orientation generation and local descriptor generation in the FG component.Our proposal can perform feature extraction of HD image with real-time efficiency of 42 fps,at a clock frequency of 100 MHz.Besides,it can roughly provide at most 2800 features per frame.Compared with other hardware solutions,it has higher resource utilization efficiency,and can provide more accurate features.The experimental results show that the features can provide robust matching across a substantial range of image changes.