Research On Accelerating Image Matching Algorithm Based On FPGA

The image feature detection algorithm is the core of image matching.Among the image feature detection algorithms,the feature points obtained by the SIFT(Scale-Invariant Feature Transform)algorithm have high robustness and accuracy.The invariance of rotation and scale transformation has a strong stability to the influence of illumination and noise.The SIFT algorithm is a serial operation structure.The algorithm has many steps and complicated calculations.In ordinary serial processors,it usually takes a lot of time and resources to process the algorithm.Therefore,it is necessary to increase the calculation speed of the SIFT algorithm.By improving the structure and content of the algorithm,modifying the parameters and formulas in the algorithm,and using the parallel computing power of FPGA(Field Programmable Gate Array)to accelerate the algorithm is currently an important research direction.The thesis studies the design and implementation of FPGA-based image matching algorithm acceleration.The main research contents are as follows:The basic principle of SIFT algorithm is analyzed,and the algorithm is divided into four parts: the establishment of image scale space,key point detection and accurate positioning,key point main direction determination and key point descriptor generation.Part of the algorithm has been improved,including dimensionality reduction of the Gaussian scale space of the SIFT image,which solves the problem of insufficient memory resources;in the Gaussian filtering process,the image is separated and filtered to double the filtering speed;for key point detection The problem of the large number of unstable feature points improves the conditions of data comparison in extreme value detection,and a method of removing bunching points in the region is proposed to filter out a large number of extreme points with poor performance.In order to improve the calculation speed of descriptor similarity,FPGA uses multiple memories to save these descriptors in batches,and read multiple descriptors at a time to perform similarity calculation,which can effectively improve the calculation speed.In order to verify the above improved method,a matching system architecture is designed.The overall hardware framework for verifying the matching algorithm is designed,and the host computer is designed on the computer and communicates with the FPGA through the serial port,realizing real-time control and verification of the algorithm.The results of the accelerated SIFT algorithm on the FPGA show that by accelerating the improved SIFT algorithm,the matching speed of the image is significantly increased,and the number of matched feature points also meets the actual needs.