CT Image Reconstruction Acceleration Research Based On FPGA

Computerized Tomography is widely used in industrial inspection and medicaldiagnostics as an important method of non-destructive testing. With the improvementsof computer technology, precision machinery and detector technology, the spatialresolution and scan speed have been greatly improved, the size and resolution of thereconstructed image also have increased, but the massive projection data bring a lot ofpressure to the transmission system, and a huge computation complexity make thereconstruction time was great, so the traditional reconstruction can not meet therequirements of real-time reconstruction. How to improve the speed of CT imagereconstruction has been a hot pot. Due to hardware limitations, software accelerationeffect is limited, so hardware acceleration technology has begun to attract people’sattention. FPGA(Field Programmable Gate Array) has become a high-performancedigital signal processing acceleration components with continuous development, theunique architecture and abundant logic resources make it suit to the parallelprocessing and pipeline design, and achieving higher processing speed.In this paper, the classical analytic CT image reconstruction algorithm isimplemented hardware acceleration on FPGA. Firstly, the algorithm was divided intosome basic functional units。With the parallel feature of each unit based on theprojection angle, the multi-pipeline parallel processing architecture was designed, andaccording to the formula of the algorithm, the hardware implementation architectureof the functional units was presented. The efficient use of IP cores reduced the designcomplexity and enhanced system reliability. The loss of accuracy for fixed-pointarithmetic was decreased by using a fixed-point grading method. Simulation resultsshow that: FPGA-based hardware reconstruction system obtaining a higher speedupwith no longer loss of image reconstruction accuracy, which verified the feasibility ofthe method. Currently, cone-beam CT has been the mainstream application, so theFPGA-based implementation of the FDK algorithm is presented. By decompositionand performance analysis of the algorithm, the pipeline processing structure wasdesigned, and the largest time-consuming back-projection unit was designed as aprojection-based multi-channel parallel processing structure; every unit uses pipelineprocessing method, so that while the system is running up, it could update areconstruction pixel in a clock-cycle. Large-scale data can not be written intoprocessing pipeline at times, so a strategy of data partition is proposed. Finallysimulation implementation, and software reconstruction results compared to the lossof the structure within the range of accuracy, get higher times speedup.