Design And Verification Of A New Anti-radiation SRAM

In the background of localization of key electronic components,and with our country doing more and more space exploration in recent years,especially under the increasing demand for anti-radiation integrated circuit,our aerospace digital logic device’s independent design also in full swing.Since the actual application process, complex space radiation environment is very easy to make memory circuit which is an important part of an integrated circuit occurs SEU.Topic source of this paper is to solve a practical aerospace SRAM functional failure occurs with domestic issues.This paper is mainly on the design of a new independent anti-radiation static memory cell with twelve transistors.On the basis of the ordinary six storage units,we use two always turned on NMOS transistors and always turned on PMOS transistors to connect to the bottomNMOS and top PMOS transistor separately. With this way, we can think we introduce four transistors on the path of the feedback signal,thus increacing the feedback time.Moreover,we introduce two symmetrical NMOS transistors with their source and drain connected on the gate of bottom NMOS transistor and PMOS transistor,and their gate is connected to the complementary output of the memory structure. Then further increased the feedback time which is needed to flip the storage state.In order to verify the double protected new anti-radiation structure,we use Sentaurus simulation software to simulate the anti radiation ability of the new SRAM storage unit through the device/circuit mixed simulation manner. The results show that the new structure’s anti-irradiation level increased 14.31 times than the traditional 6 transistor structure, linear energy transfer threshold value reachs 52.95Me V·cm2/mg.We have also simulated the read time and write time,read and write power consumption,as a comparison,the other three storage units’corresponding performance have been simulated too.The results show that the new unit’s reading and writing time needs further improvement in order to be better applied to the actual SRAM designs.Then,based on this new storage unit,using SMIC 130nm standard CMOS technology library constructed asynchronous operation mode SRAM with a size of 512x8bit.For the 512×8bit size storage arrays,I build its peripheral circuits.Peripheral circuit includes a row decoder,a column decoder,a row decoder driver,data distributor,ATD circuit,precharge circuit, amplifier,single-end double-end transformer,read and write control signal generation module, EDAC module.EDAC module realizes the detect and correct a stored data flip function,thereby further enhancing the radiation level of the SRAM chip. As the SRAM control signal generation module,ATD circuit generate the precharge signal and the amplify enable signal automaticly by detecting changes in the address signal,which greatly reduces the power consumption of the SRAM,what’s more,simplifies the SRAM timing control for read and write operations.In the design section of each peripheral circuit,simulation results are given for some key modules.Finally,I use spectreverilog software simulate the whole SRAM’s function in a manner of digital-analog hybrid simulation. Randomly writing eight points, follo wed by reading out the eight points,the results show that the memory can correctly work with 13ns write time and 16ns read time,then the operating frequency can be considered equivalent to 62.5Mhz.When joining the EDAC module,writing time increases to 14ns and reading time increases to 19ns.Under this circumstance,EDAC module can correctly detect and correct one bit storage data tipping. The SRAM’s power is 30.993 mW during the time of writing and reading one data, which can meet the low power requirements.