| Floating-point Fuse Multiply-add(FMA)component is one of the core components of high performance processors,and its performance determines the performance of high performance processors.The study of high performance FMA components has become a hot spot at home and abroad.With the increasingly stringent requirements for high-performance computing in various modern devices,the design and research of floating-point units have become very popular.However,due to the limited space resources of the chip,a large number of independent precision floating point computing units are bound to occupy a large number of hardware resources.Therefore,the research on the fused precision floating point units has become the current development trend.Especially in recent years,the development of artificial intelligence is very rapid,and its demand for floating point arithmetic is also increasing,which further stimulates the research of FMA units.In addition,most of the application scenarios do not require high precision,single precision can meet the requirements,even some only need half precision arithmetic,and low precision has more efficient arithmetic speed.Therefore,it is important to realize the arithmetic performance of higher single-precision and semi-precision floating-point,design smaller chip area and lower arithmetic power consumption,and design the components applied for multiple scene.In this thesis,a mixed precision floating-point multiplication structure of stage 3assembly line was realized,which supported various floating-point arithmetics such as addition and subtraction,multiplication,copy,and comparison of multi-precision floating-points.In this paper,the traditional Fuse Multiply-add structure is improved to realize the floating point single precision three-phase flow-shop floating point multiply-add units structure with high performance and low power consumption,and the high sharing design of key hardware is used to integrate the half precision floating point arithmetic into it.A logic multiplexing method was proposed for multiplier,shifter,and odd predictor for semi-precision data and single-precision data,which reduced the chip area and the arithmetic power consumption.In the design of the key module multiplier,the second-order Booth arithmetic is improved,and the final part of the product is implemented by using the improved arithmetic,and the parallel compression processing is carried out,which effectively improves the parallelism of the design and reduces the delay of floating point units.And when the adder module is summing up,by using the end around carry adder,one additive is reduced,and the purpose of reducing the delay is realized again.By using the method of shift in advance,the shift device has reduced the occurrence of shift and the steps of shift,and has also improved the shift efficiency,and single precision and half precision floating point share shift device has reduced the waste of hardware resources.At the same time,the logic resources such as multiplication,shift and addition of floating-point multiplication structure were modularly reorganized in this paper.The dual path structure of floating-point path and integer expansion path was adopted,and the traditional 32 * 32 array structure was discarded.Floating-point path adopts 24*24 array to realize single and semi-precision floating point operation independently.Integer extended path is divided into two parts,8*32 array structure and 24*8array structure.Integer operation is completed with the cooperation of floating point path.This structure not only supported multi-precision floating-point multiplication arithmetics,but also supported many types of integer multiplication arithmetics,which further expanded the application scenario of hybrid precision floating-point multiplication.The Spyglass code detection tool and floating point small environment library provided by the training unit were used to check the syntax error and verify the function of the design code.Based on the specific process database provided by the training unit,the DC comprehensive results showed that the typical working frequency of the structure reached more than 1 GHz when it was only used for floating-point arithmetic,which could save25.28% of structure area and 23.59% of power consumption compared with that of traditional multi-set floating point operation unit. |
