Implementation And Verification Of Hash Algorithm

With the rapid development of internet of things technology,the security of data such as personal privacy in the process of information transmission has been seriously threatened,and the research on information security has gradually attracted more and more researchers.As the basis of information security,cryptography can guarantee the confidentiality,integrity,and resistance to attacks in the process of information transmission.Hash algorithm is a kind of cryptographic algorithm.It is a one-way hash function with irreversible characteristics.With this characteristic,the hash algorithm can be applied to scenarios such as data integrity verification,unique identification,and digital signature.In recent years,with the development of cryptography,hash algorithms have developed a variety of types,including MD5,SHA-1,SHA-2,SHA-3 and SM3.SHA-2,SHA-3 and SM3 are the current mainstream hash algorithms.In this paper,according to different application scenarios,combined with domestic and international hash algorithm standards,SM3 and SHA-3 algorithms are selected to design.The final design results basically realize the optimization of hardware module area,and the hardware reuse design of SM3 and SHA-3 algorithms is the innovation of this paper.The main contents are as follows:(1)Aiming at the algorithm hardware design,this article focuses on the area optimization under the condition that the speed meets certain requirements.In the process,first of all,combined with the idea of software and hardware co-design,the SM3 and SHA-3 algorithm data filling part is realized by software,which not only saves area resources,but also improves the flexibility of the algorithm;secondly,through time division multiplexing and optimized addition The method such as the device and split pipeline reduces the number of logic devices such as registers,and realizes the optimization of the area;finally,the hardware structure reuse method is used to realize the reuse design of SM3 and SHA-3 algorithms.(2)In terms of functional verification,the VCS simulation debugging software of Synopsys company is used to carry out the pre-simulation test of the algorithm hardware module at the module level and system level,and the FMX7 A development board is used to verify the FPGA board level.The results show that the hardware module has normal function through simulation test and board level verification.(3)In the comprehensive performance analysis,based on SMIC 55nm process,the algorithm modules are synthesized using DC logic synthesis tools.When the frequencies are500MHz and 200MHz,the results show that the area of SM3 and SHA-3 modules are253088)~2 and 621068)~2,respectively,and the throughput rates have reached 1.7Gbps and12.4Gbps,respectively.After comparing with other designs,it can be found that the area of SM3 and SHA-3 algorithm modules is the best,and the frequency and throughput rate also have certain advantages.In addition,the combined area of SM3 and SHA-3 multiplexing hardware design is about 730848)~2.It can be seen that the multiplexing structure has great advantages in area,and the speed and throughput rate basically meet the requirements.The results are generally in line with expectations.