Research And Implementation Of Secure Hash Algorithm In Embedded System

Secure Hash Algorithm has the feature of fast computing speed and lowarea, which are widely used in digital signatures, message authenti cation, andRadio Frequency Identification (RFID). With the development of cryptanalysisand the traditional hash algorithm SHA-0, SHA-1, etc. have been successfullyattacked; NIST promotes to develop a new generation of hash algorithm (SHA-3) to adapt to the development of information security. With the requirementsof faster speed, smaller area and lower power consumption for hardware basedcryptogrtaphic algorithms, the performance parameters like area, frequency,throughput, and power consumption become the optimized goals for SHA-3onhardware platform. The shortcomings of the existing hardware implementionfor SHA-3candidate algorithms are:1) the hardware implementation of thehash algorithm lacks of flexibility;2) the throughput and area of hardawa rebased hash algorithm need to be improved;3) the existing hardwareimplementation lacks of the parameter of power consumption. In order tosovle the above problem, this article proposed three different hash algorithmsbased on hardware platform accordin g to the application requirements ofEmbedded system.First of all, this paper proposed a new JH algorithm structure based onhardware platform. Based on the hardware reprogrammable features of FPGA,the proposed design has a reasonable division of the fun ction modules andoptimized the critical part of the JH algorithm through the methodology ofdynamic partially reconfigurable technology. This design flexibily supportsJH-224, JH-256, JH-384and JH-512four different designs， and thethroughput to area ratio increased more than118%of the existing design whenported to Xilinx Virtex-5FPGA platform, which has a better overallperformance.Furthermore, this paper proposed a low-power hardware implementationof JH algorithm for RFID application. This article proposed a16-bits widthround function structure， which has slower operating frequency and lowerarea occupication. The proposed low-power JH-256hardware implementationusing27.8859μW when ported to ASIC0.18μm CMOS technology running at 100KHz; and the proposed design takes up24797gate equivalents, getting51.5%lower than existing design.Last but not least, this paper proposed a low-power hardwareimplementation of KECCAK algorithm for RFID applications. This articleoptimized the hardware architecture of the KECCAK algorithm through use ofthe external storage; and divided a long combinational logic circuit intoseveral calculation cycles to shorten the critical path; and makes the use ofmodule reusing technology to reduce the design area. The proposed low-powerKECCAK hardware implementation using27.03μW when ported to ASIC0.18μm CMOS technology running at100KHz, getting39%lower thanexisting design; and the proposed design takes up4200gate equivalents,having certain advantages when compared with the existing designs.