Research And Implementation Of High Performance Multiplexing Hash Algorithm For IoT Security

With the rapid development of the Internet of Things(IoT)and the popularity of related applications,security issues such as privacy breaches and intrusion attacks have begun to emerge.So it is significant to facilitate the security of information when we make use of the power and convenience of IoT.Hash algorithm is an indispensable part of cryptography and IoT security.It not only provides secure and reliable keys for encryption and decryption algorithms,but also is widely used in digital signatures,files and message authentication and so on.In the IoT application,depending on the application environment,the encryption and decryption algorithms that need to be used are different,so the corresponding keys and the hash algorithms are not the same.In addition,the requirement of performance,circuit area and safety of different IoT applications are different.Therefore,in order to deal with this feature and situation of IoT,this paper selects three algorithms,Haval,Whirlpool and SM3,to realize high-performance multiplexing hash algorithms circuit.And the performance of the algorithm is improved by the cycle compression structure and the pipeline structure.Compared with the separately implemented Hash algorithm circuit,it has advantages in the area and performance.In the functional test and performance analysis phase,this paper completed the functional simulation and code coverage detection of all circuit design based on Modelsim,and passed all the test.Based on the Altera FPGA DE4,the resources and performance of each circuit design were compared and analyzed.The multiplexing circuits of Haval,Whirlpool and SM3 in this paper have obvious advantages in throughput rate and circuit resource occupation compared with other literature and methods.And the maximum throughput rate of Haval,Whirlpool and SM3 circuit can achieve 4.1 Gbps,9.9 Gbps,and 3.8 Gbps.After that,the system-on-chip was built based on ARM-SC000,and the FPGA verification was accomplished using Altera's FPGA DE2.Based on the HHGrace 110 nm process,this paper carries out digital ASIC implementation,performance and resource analysis for each circuit,and completed the formal verification and static timing analysis.Compared with other related studies,the hardware implementation of the multiplexing circuit in this paper performed better in terms of throughput and circuit area.The maximum throughput rate of the most advanced circuit of Haval,Whirlpool,SM3 can respectively achieve 4.7 Gbps,7.8 Gbps,and 4 Gbps.All the circuits designed in this paper meet the design and application requirements in resource occupation and performance.