Design And Implementation Of JESD204C High Speed Serial Interface Controller Based On JESD204C Protocol

With the rapid development of electronic communications industry,systems such as medical imaging,radar communications,smart homes,and 5G small base stations have higher and higher performance requirements for data converters.Traditional interface technologies have been unable to meet today's high-speed data transmission needs.The JESD204 C protocol is the latest version of the JESD204 C series protocol released by the JEDEC Association.Its JESD204 C high-speed serial interface has the advantages of low power consumption,fewer pins,high speed,and supports deterministic latency and data error detection and correction functions.Therefore,the JESD204 C interface is gradually becoming the preferred choice for high-speed serial data transmission between data converters and FPGA/ASIC.Based on the JESD204 C protocol standard and design specifications,this thesis designs a high-speed serial interface controller suitable for data transmission between 4dual-channel,250 MSPS,14-bit ADC and FPGA/ASIC.The controller supports dualchannel transmission with a single-channel transmission rate of 16.5Gbps,supports multichannel synchronization and deterministic delay,supports subclass 0 mode and subclass1 mode,and supports CRC-12 and FEC functions.This thesis first introduces the development process of the JESD204 series of protocols and the comparison of various versions,analyses the features and advantages of JESD204 C protocol,and details the content of JESD204 C protocol.After that,the RTL design of key modules is completed on the basis of determining the whole framework.The transport layer modules realize the framing and deframing of the sampled data of the4 dual-channel,250 MSPS,14-bit analog-to-digital converters according to the mapping rules.The scrambling and descrambling modules implement a 64-bit parallel selfsynchronizing scrambling circuit and descrambling circuit,which reduce spectral peaks and reduce data bit error rate.The CRC encoding and decoding modules implement a 64-bit parallel CRC-12 encoding and decoding circuit,which improve the error detection capability of system.The FEC encoding and decoding modules implement a 64-bit parallel FEC encoding and decoding circuits,which can correct up to a 9-bit burst error per multiblock,ensuring the robustness of the system during high-speed data transmission.The sync header encoding and decoding modules implement the sync header transmission of the command signal,CRC signal and FEC signal based on the 64b/66 b encoding principle,and at the same time realize the alignment of the block boundary and the synchronization of the link.These designed circuit modules are simulated by Modelsim software to verify the functional correctness.Based on the EDA tools Vivado 2019.1 and Xilinx KC705 development board,the thesis completed the circuit design of the JESD204 C transmitter and receiver controller,verified the synthesizable code and simulated the functional correctness of the transmitter and receiver controller.Finally,a verification platform is built to simulate the transceiver system and board-level loopback verification through six verification schemes.The results show that the transceiver system has correct data transmission and complete functions.