Design And Implementation Of 3GHz Low-noise Fully Integrated Phase-locked Loop

The phase-locked loop has been widely used to generate various clock frequencies in digital-to-analog converters(DAC),digital processors as well as the high-speed links.It can track the frequency and phase of the input signal and realize the frequency synthesis by the feedback frequency divider.In the application of satellite communication and electronic radar,S-band is an important frequency band for downstream signals.It is necessary to ensure a wide tuning range and low lock time of its clock source to achieve the controllable scanning range of frequency and the fast switching between different channels.At the same time,optimizing the non-ideal factors of its clock source(such as jitter and noise)is also critical to the entire system.This article aims at the vacancy of the S-band ultra-low noise frequency synthesis chip in the domestic market.By optimizing the noise of each module,the design realizes a low-noise full integration phase-locked loop chip with a center frequency of 3 GHz and a frequency coverage of 2.8-3.2 GHz.Moreover,the tape-out verification meets the design requirements.This paper derives the dynamic characteristics of the phase-locked loop when it is close to lock in detail by establishing a linear approximation model of the phase-locked loop.Based on this,the influence of the noise introduced by each sub-module on the overall phase noise of the phase-locked loop is analyzed,and the noise optimization scheme for each module is specifically proposed to guide the circuit design.Taking advantage of the high-speed and high common-mode rejection ratio of the logic gate of the current-mode architecture,this paper proposes a new high-speed prescaler of 2?8frequency division with 50% duty cycle.The frequency multiplier module is added to the reference input channel to obtain a higher phase discrimination frequency,resulting in better noise characteristics when the input frequency is lower.The voltage-controlled oscillator adopts an active LC structure with negative resistance and uses LDO to power it separately to suppress the power supply rejection ratio.A frequency self-calibration algorithm is proposed to obtain a wider lock frequency range and faster lock time.The VCO and LPF are integrated on chip,and the expansion port is reserved for adjustable bandwidth.Based on the 0.18?m Si Ge Bi CMOS process,this paper simulates and verifies the functional realization and phase noise of each module in the circuit.Finally,the whole chip is tested and verified,resulting that the phase-locked loop designed in this paper can achieve frequency synthesis near the 3GHz center frequency,the phase noise floor of the phase-locked loop band is-223 d Bc/Hz,and the integrated jitter of 12 k Hz-20 MHz is127.5fs.