Research And Design On Voltage Controlled Oscillator And Phase-Locked Loop

Phase-locked Loop(PLL)can provide a stable frequency source,which plays an important role in communication system.The performance of PLL has a significant influence on communication system,especially the phase noise of PLL.As an important module in PLL,Voltage Controlled Oscillator determines the phase noise of PLL greatly.The performance of PLL can be seriously affected by power supply,so PLL's power supply provided by Low Dropout Regulator(LDO)generally.This paper shows the theoretical bases,transfer function,and phase noise of PLL.Basing on theoretical analysis,Charge Pump Phase-locked Loop(CPPL)is decided to use in this paper.Aiming at the design of VCO,this paper shows the theoretical bases,model of phase noise and noise source of VCO.According to the theoretical analysis and actual demand,the structure of VCO is decided.Then the parameters of circuit are optimized.Lastly,several methods are used to optimize the performance of phase noise.Aiming at the demands for power supply,a capacitor-free transient-enhanced LDO is designed for PLL.By sensing the voltage variation of output voltage of LDO and providing additional current in LDO by high speed transconductance amplifier,the performance of transient response can be enhanced.Also,this paper proposed a low temperature coefficient high power supply rejection ratio bandgap reference which can offer a high precision voltage for LDO.Basing on Cadence and 0.18 um technology,the circuit was simulated using spectre emulator.Powered by LDO which provides a 1.6V supply,VCO's double side output amplitude is 1.6V and its waveform is well.The phase noise is-117.6dBc/Hz and-128.5dBc/Hz at 1MHz and 3MHz offset from 10GHz.The frequency band can be tuned from 9.5251GHz to 11.2367GHz.Under 1.8V power supply,the proposed bandgap reference features a temperature coefficient of 1.34ppm/? from-40? to 120?,a PSRR of-127dB at low frequencies,-98dB at 100KHz,-67dB at 1MHz,and LDO can work stably with 1.6V output voltage,10pF load capacitor and 0-100mA load current.The undershoot voltage and overshoot voltage for a load current of 1-100mA are 72mV and 42mV.And the settling time is less than 1.5us.The simulation shows,when the input crystal oscillator frequency is 25MHz,PLL's output signal frequency is 10GHz with settling time is 5us.