Design Of Phase-locked Loops Circutes For Generating Clock Signal

So C often integrated a lot of functional blocks, each requiring a specific clock frequency. But, a fixed reference crystal is provided to generate the required frequencies. So, a phase locked loop for generating clock signal is needed for So C.In this paper, the design of fully integrated charge pump phase locked loop(CPPLL) is used for generating clock signal, input frequency range is 5~50MHz and output frequency range is 250~500MHz.This paper first builds the mathematical model for every module based on the basic structure of the CPPLL, and builds the top math model for the CPPLL system and completes the calculation of the system parameters of the model according to the design index. Then this paper establishes behavior model for CPPLL, simulates and verifies the calculated system parameter in the behavior model. After that, this paper introduces the design process of the circuits of the module in the CPPLL emphatically, and completes corresponding analysis and consideration. This paper puts forward the circuit structure of second order switch low-pass filter to improve the locking performance of the PLL. With the traditional second order loop filter replaced by this structure, the locking time of the loop can be shortened. This paper also simulates the peak-peak jitter of the PLL caused by the substrate noise and the phase noise of the PLL.This paper implements the PLL circuit based on the SMIC 0.18μm, and completes the layout and the post-simulation. When the carrier frequency of the PLL output is 500 MHz, the phase noise of the PLL respectively at an offset frequency of 1MHz is-97.6901 d Bc@1MHz.