The PLL Circuit Design In Microgyroscope

Phase-Locked Loops(PLL) is a fundamental and very important building block in analog and mixed-signal integrated circuits. Phase-locked system can track the input signal phase and frequency, output phase-locked and low fitter other frequency signals. In most system application, PLLs server as a powerful technical course to afford perfect resolve method.This article designs a Charge-Pump PLL(CPPLL) with high-performance used in microgyroscope under CSMC 0.6μm technics. It studies phase noise and loop performance, and then the PLL circuit is simulated in detail. Finally, layout and post-simulation are completed. The main application of the PLL for microgyroscope to provide a stable high frequency carrier signal drivers.The circuit using standard CMOS CPPLL structure, including Phase Frequency Detector(PFD), Charge Pump(CP), Low Pass Filter(LPF), Voltage Controlled Oscillator(VCO) and Frequency Divider(Divider) five modules. First, this paper is introduced from development of PLL, then from the PLL sub module, detailed analysis of each module and the advantages and disadvantages of working principles, and gives optimization program, at last, draws the layout. Throughout the design used to overcome the dead-zone phase frequency detector structure, elimination of the charge injection and charge sharing of self pumps structure, the use of better noise characteristics, wide output frequency, clock signal duty cycle accurate CSA VCO structure and the use of high-speed TSPC structure.Simulation results show that the output frequency jitter:ΔF P ?P=7.4844Hz, cycle jitter: ps, Relative jitter: 0.0299‰. Compare with the previous RC ring oscillator as a reference signal, the performance was greatly improved. This is very important for microgyroscope to improve the measurement accuracy and overall circuit performance.ΔT P?P=119.75...