Design Of Charge Pump PLL Based On The Full Differential Ring Oscillator

With the development of science and technology, the integrated circuit has been widely used in portable electronic devices, computers, digital television, satellite communications, aerospace, and remote control, etc. As the clock source of integrated circuit especially the mixed circuit, frequency synthesis technology becomes more and more important. The simple circuit and good performance of PLL frequency synthesis technology make it developed rapidly. The frequencies produced by this method have the qualities of good stability, strong spurious suppression and good anti-noise performance. The purpose of this paper is to design the PLL frequency synthesis circuit of image sensor chip.First, in this easy, the basic principle, the topological structure and the linear model of charge pump phase-locked loop is analyzed. Based on the basic principles, the closed loop characteristic analysis, the open loop characteristic analysis, the locking performance analysis and stability analysis is also made. In order to suppress the influence of noise of each module on the output frequency and to suppress the phase noise of PLL system, the noise transfer characteristics of the system is analysed. These works has a very good guidance in setting parameters and optimize performance and so on. Then by selecting and analyzing every module, and considering the possible non-ideal factors of each module of the PLL system, the module circuit of PLL that meets the demand of the system is designed and have pass the verification. The paper focuses on the design of a ring oscillator with differential structure, which uses the delay unit structure of symmetrical load and the self-biased structure. This help to improve power supply noise, common mode noise and phase noise suppression performance. By using the buffer circuit, the differential output waveform of oscillator delay unit is converted to a 50% duty cycle square wave clock. Simulation results show that the ring VCO has low phase noise performance and meet the requirements of PLL system. After completing all the module circuit design, the next step is to verify the whole PLL circuit, including: verifying the stability of the system with matlab; verifying capture performance with spectre tool; estimating the system phase noise through the establishment of noise model and so on. The simulation results show that: the PLL has 100M~500MHz output frequency range; lock time at each operating frequency is less than 20us; the phase noise of PLL is-113MHz@10MHz; and RMS Jitter is less than 2% of clock cycle. The charge pump phase-locked loop can be quickly locked, work steadily in the required frequency range, and is in line with the requirements of frequency synthesizer of image sensor.In the end, the scheme of phase-locked loop layout and key points are described. The circuit and layout design of PLL are based on SMIC 0.18μm CMOS Process, and will be applied to image sensors for tape-out.