Design And Implementation Of High Speed DDS Based 65nm

Direct Digital Frequency Synthesizer(DDS)is a key unit in contemporary electronic systems.Because of its high-performance frequency output and fast frequency switching capabilities,it is widely used in modern communication systems,radar systems and many high-precision measuring instruments,etc.With the continuous progress of manufacturing technology,the size of integrated circuits is getting smaller and smaller.DDS designed for Application Specific Integrated Circuit(ASIC)has been more and more researched and manufactured.For example,the fifth generation mobile communication technology(5G),Multiple-in Multiple-out(MIMO)and other cutting-edge technologies are playing an increasingly important role.Based on the project requirements,this article designs and implements the high-speed DDS digital unit based on the Taiwan Semiconductor Manufacturing Company(TMSC)65nm process.First,the high-speed parallel structure of the digital unit and the core phase-amplitude conversion circuit are deeply studied,and the corresponding MATLAB simulation analysis is completed.At the same time,the phase-amplitude conversion algorithm adopted has been improved and optimized in the specific realization of the circuit,which makes it more suitable for the structural design of high-speed circuits while reducing the area.This text has carried on the realization and verification to the DDS digital unit circuit designed in the hardware,its overall DDS digital unit output data rate reaches 6Gsps.At the same time,according to the back-end digital-to-analog converter(DAC)structure,a circuit structure based on interpolation and modulation is designed and implemented so that the digital front end can complete 12Gsps data output.Finally,it was verified that the Spurious Free Dynamic Range(SFDR)of the full frequency band of its digital unit reached 85dB,which met the design requirements of high-speed and high-performance DDS.This paper also further researches and designs the key units involved in the design of high-speed DDS chips.In high-speed design,in order to ensure the stability and reliability of the overall DDS clock architecture,and to ensure the correctness of data in the process of digital-analog interaction,The Delay Locked Loop(DLL)search algorithm in DLL is researched and designed.At the same time,in view of the problem of low output performance caused by the mismatch error of the current-steering DAC,dynamic element matching(DEM)has also been continuously researched and designed.This article first compares and analyzes the different DEM implementation structures,and finally designs and implements the DEM circuit.Finally,this article designs and implements the overall SPI interface,and prototypes the overall control flow to ensure the correct function of the control part of the digital unit.In this paper,based on the TSMC 65nm process,the DDS digital unit is designed and verified at the back end,and related work such as logic synthesis,formal verification,and placement and routing is completed.From the perspective of ASIC design,the timing closure and the design rule check(DRC)is completed.We obtained the preliminary area,power consumption and timing report,completed the preliminary timing and DRC verification process,and finally completed the design and delivery of the entire digital unit.