Research And Implement Of Timing Synchronization And Blind Equalization Of High-order QAM Signal Demodulation

With the rapid development of VLSI technology,people's access to data changes with each passing day.The traditional serial information processing method has been stretched out in the face of high-capacity and high-speed data.Digital parallel processing has become a research hotspot and development trend.Quadrature amplitude modulation(QAM)is used in high-speed data transmission system because of its high frequency band utilization.The performance of a parallel digital receiver system also depends on the structure of the receiver.At the same time,the Timing Synchronization and Equalization module is an indispensable part of the whole digital demodulation system.Firstly,starting from the structure of parallel digital receiver.As a mature parallel digital receiver structure,APRX architecture has been proved to be almost the same in bit error rate performance compared with serial receiver,and the way of parallelizing data processing reduces the requirements for hardware timing,which has good engineering implementation.Therefore,this architecture is selected as the high-speed parallel digital demodulation structure in Thesis.The Timing Synchronization module is designed from the selection of algorithm.After analyzing the feedforward algorithm based on maximum likelihood estimation,the O?M algorithm is finally used as the core algorithm of the timing synchronization module,and a 32 channel parallel feedforward Timing Synchronization module is designed based on the high-speed parallel digital demodulation structure.After analyzing the influence of modulation mode and channel on high-speed wireless communication system,it is determined that the Equalization module adopts 8-channel parallel blind equalization algorithm.Several classical constant(multi)modulus and their improved algorithms are analyzed.After analyzing their advantages and disadvantages,the MMA blind equalization algorithm suitable for highorder QAM modulation is adopted,and the variable step size MMA algorithm is designed.Then,the performance of the designed O?M feedforward timing synchronization module under different frequency offset is simulated by MATLAB from three aspects:constellation before and after timing,phase offset correction factor and frequency offset control enabling,which verifies the correctness of the module design.At the same time,taking CMA algorithm and MMA algorithm as the comparison algorithms,the designed variable step size MMA algorithm can be simulated from the aspects of constellation before and after equalization,steady-state error and convergence speed.The results show that the variable step size MMA algorithm is better than the traditional CMA algorithm and MMA algorithm.Finally,the simulation platform is built based on FPGA,AD9371 and AD9528,and Verilog HDL is written.The parallel timing synchronization module and adaptive blind equalization module are verified at the board level.The experimental results show that under 64 QAM modulation,the feedforward O?M parallel timing synchronization scheme designed in thesis has the ability to correct the timing frequency offset of 200 ppm,and the steady-state error after the convergence of the adaptive blind equalization module is no more than-18 d B,which achieves the expected research goal.